diff options
| author | Michal Simek <[email protected]> | 2025-09-22 10:28:15 +0200 |
|---|---|---|
| committer | Michal Simek <[email protected]> | 2025-10-09 09:07:04 +0200 |
| commit | 145645a9f29121c7ee3fb36abe87a9c6dc9f25e3 (patch) | |
| tree | 23f1697d8f974df2cf0df629724b99b5c07ff6d2 | |
| parent | 68dc66d7e06690784ad36d1d930acd7f4f2cbceb (diff) | |
arm64: zynqmp: Fix DTOVL warning about graphs in kv/kr260
DTC is generating warnings about missing port like:
DTOVL arch/arm/dts/zynqmp-smk-k24-revA-sck-kv-g-revB.dtb
arch/arm/dts/zynqmp-sck-kv-g-revA.dtbo: Warning (graph_port):
/fragment@5/__overlay__: graph port node name should be 'port'
...
That's why change description and add it directly to dpsub mode to contain
full description with also port.
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/576630cc9696e21bef15bd1f0ca35e396adc4eca.1758529693.git.michal.simek@amd.com
| -rw-r--r-- | arch/arm/dts/zynqmp-sck-kr-g-revA.dtso | 10 | ||||
| -rw-r--r-- | arch/arm/dts/zynqmp-sck-kr-g-revB.dtso | 10 | ||||
| -rw-r--r-- | arch/arm/dts/zynqmp-sck-kv-g-revA.dtso | 12 | ||||
| -rw-r--r-- | arch/arm/dts/zynqmp-sck-kv-g-revB.dtso | 12 |
4 files changed, 26 insertions, 18 deletions
diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso index b92dcb86e87..88396d089f4 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revA.dtso @@ -154,11 +154,13 @@ phy-names = "dp-phy0"; phys = <&psgtr 1 PHY_TYPE_DP 0 1>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; -}; -&out_dp { - dpsub_dp_out: endpoint { - remote-endpoint = <&dpcon_in>; + ports { + out_dp: port@5 { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; + }; }; }; diff --git a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso index 99ad220d13d..e041a962d89 100644 --- a/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kr-g-revB.dtso @@ -155,11 +155,13 @@ phy-names = "dp-phy0"; phys = <&psgtr 1 PHY_TYPE_DP 0 1>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; -}; -&out_dp { - dpsub_dp_out: endpoint { - remote-endpoint = <&dpcon_in>; + ports { + out_dp: port@5 { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; + }; }; }; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso index d7351a17d3e..fbbebbea80c 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revA.dtso @@ -3,7 +3,7 @@ * dts file for KV260 revA Carrier Card * * (C) Copyright 2020 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. * * SD level shifter: * "A" - A01 board un-modified (NXP) @@ -131,11 +131,13 @@ phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; -}; -&out_dp { - dpsub_dp_out: endpoint { - remote-endpoint = <&dpcon_in>; + ports { + out_dp: port@5 { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; + }; }; }; diff --git a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso index a4ae37ebacc..87f94f8ef9d 100644 --- a/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso +++ b/arch/arm/dts/zynqmp-sck-kv-g-revB.dtso @@ -3,7 +3,7 @@ * dts file for KV260 revA Carrier Card * * (C) Copyright 2020 - 2022, Xilinx, Inc. - * (C) Copyright 2022 - 2023, Advanced Micro Devices, Inc. + * (C) Copyright 2022 - 2025, Advanced Micro Devices, Inc. * * Michal Simek <[email protected]> */ @@ -116,11 +116,13 @@ phy-names = "dp-phy0", "dp-phy1"; phys = <&psgtr 1 PHY_TYPE_DP 0 0>, <&psgtr 0 PHY_TYPE_DP 1 0>; assigned-clock-rates = <27000000>, <25000000>, <300000000>; -}; -&out_dp { - dpsub_dp_out: endpoint { - remote-endpoint = <&dpcon_in>; + ports { + out_dp: port@5 { + dpsub_dp_out: endpoint { + remote-endpoint = <&dpcon_in>; + }; + }; }; }; |