diff options
| author | Ajay Kumar <[email protected]> | 2013-01-08 20:42:23 +0000 |
|---|---|---|
| committer | Minkyu Kang <[email protected]> | 2013-01-10 10:19:47 +0900 |
| commit | 1673f199d917e0649098e0cb7ef5b375b96bd6cb (patch) | |
| tree | 827f9a574affebaab94e75ee1f909585f4c2357b | |
| parent | 9b572852c0547365b186651d27b3df5dcbe82be2 (diff) | |
EXYNOS5: Change parent clock of FIMD to MPLL
With VPLL as source clock to FIMD,
Exynos DP Initializaton was failing sometimes with unstable clock.
Changing FIMD source to MPLL resolves this issue.
Signed-off-by: Ajay Kumar <[email protected]>
Acked-by: Simon Glass <[email protected]>
Acked-by: Donghwa Lee <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
| -rw-r--r-- | arch/arm/cpu/armv7/exynos/clock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index ae6d7fe0d9b..abc327262a4 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -741,7 +741,7 @@ void exynos5_set_lcd_clk(void) */ cfg = readl(&clk->src_disp1_0); cfg &= ~(0xf); - cfg |= 0x8; + cfg |= 0x6; writel(cfg, &clk->src_disp1_0); /* |