diff options
| author | Jonas Karlman <[email protected]> | 2024-04-22 06:28:38 +0000 |
|---|---|---|
| committer | Kever Yang <[email protected]> | 2024-04-26 15:47:03 +0800 |
| commit | 19bf563304f2024451d5d04d4a7f0e8b73eabd7d (patch) | |
| tree | 22143f8747f444011c2747d1559390e1abb7c9b8 | |
| parent | c5b8eaff632e8c46f77ba1587568a698a5b6f039 (diff) | |
clk: rockchip: rk356x: Add CLK_USB3OTGx_REF support
The CLK_USB3OTGx_REF clocks is used as reference clock for USB3 block.
Add simple support to get rate of CLK_USB3OTGx_REF clocks to fix
reference clock period configuration.
Signed-off-by: Jonas Karlman <[email protected]>
Acked-by: Sean Anderson <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
| -rw-r--r-- | drivers/clk/rockchip/clk_rk3568.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/clk/rockchip/clk_rk3568.c b/drivers/clk/rockchip/clk_rk3568.c index 57ef27dda89..999f48ea4b4 100644 --- a/drivers/clk/rockchip/clk_rk3568.c +++ b/drivers/clk/rockchip/clk_rk3568.c @@ -2417,6 +2417,8 @@ static ulong rk3568_clk_get_rate(struct clk *clk) case BCLK_EMMC: rate = rk3568_emmc_get_bclk(priv); break; + case CLK_USB3OTG0_REF: + case CLK_USB3OTG1_REF: case TCLK_EMMC: rate = OSC_HZ; break; @@ -2596,6 +2598,8 @@ static ulong rk3568_clk_set_rate(struct clk *clk, ulong rate) case BCLK_EMMC: ret = rk3568_emmc_set_bclk(priv, rate); break; + case CLK_USB3OTG0_REF: + case CLK_USB3OTG1_REF: case TCLK_EMMC: ret = OSC_HZ; break; |