diff options
| author | Neil Armstrong <[email protected]> | 2025-05-02 08:51:45 +0200 |
|---|---|---|
| committer | Neil Armstrong <[email protected]> | 2025-09-30 20:32:15 +0200 |
| commit | 1a367adfd66c28d8d2fdb2957dfba5434b987de1 (patch) | |
| tree | 2eaf694031516d8e4796cd25cdaf2c06f85c978a | |
| parent | 9710d98e8942151fc0c62d54100d9d27e8263d04 (diff) | |
net: mdio: mux-meson-gxl: set reversed bit when using internal phy
This bit is necessary to receive packets from the internal PHY.
Without this bit set, no activity occurs on the interface.
Normally u-boot sets this bit, but if u-boot is compiled without
net support, the interface will be up but without any activity.
The vendor SDK sets this bit along with the PHY_ID bits.
Ported from the Linux change at [1] from Da Xu merged in
commit [2].
[1] https://lore.kernel.org/all/[email protected]/
[2] b23285e93bef ("net: mdio: mux-meson-gxl: set reversed bit when using internal phy")
Suggested-by: Da Xue <[email protected]>
Link: https://lore.kernel.org/r/20250502-u-boot-topic-mdio-mux-gxl-bit28-v1-1-399f6c3db154@linaro.org
Signed-off-by: Neil Armstrong <[email protected]>
| -rw-r--r-- | drivers/net/mdio_mux_meson_gxl.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/drivers/net/mdio_mux_meson_gxl.c b/drivers/net/mdio_mux_meson_gxl.c index 8ef3ae598b7..31898ed437e 100644 --- a/drivers/net/mdio_mux_meson_gxl.c +++ b/drivers/net/mdio_mux_meson_gxl.c @@ -19,6 +19,7 @@ #define REG2_LEDACT GENMASK(23, 22) #define REG2_LEDLINK GENMASK(25, 24) #define REG2_DIV4SEL BIT(27) +#define REG2_REVERSED BIT(28) #define REG2_ADCBYPASS BIT(30) #define REG2_CLKINSEL BIT(31) #define ETH_REG3 0x4 @@ -66,7 +67,7 @@ static int meson_gxl_enable_internal_mdio(struct mdio_mux_meson_gxl_priv *priv) * The only constraint is that it must match the one in * drivers/net/phy/meson-gxl.c to properly match the PHY. */ - writel(FIELD_PREP(REG2_PHYID, EPHY_GXL_ID), + writel(REG2_REVERSED | FIELD_PREP(REG2_PHYID, EPHY_GXL_ID), priv->regs + ETH_REG2); /* Enable the internal phy */ |