diff options
| author | Ye Li <[email protected]> | 2024-09-19 12:01:29 +0800 |
|---|---|---|
| committer | Fabio Estevam <[email protected]> | 2024-09-19 00:12:41 -0300 |
| commit | 1b631589d4844a129e1019160fef7aeda6fb50ff (patch) | |
| tree | d7106fbee391b693c81cefec6094d74d95b13940 | |
| parent | ab7566d78b6bb6a0c4ba49c8bd866f7b98abb309 (diff) | |
imx9: Add 233Mhz DDR PLL frequency
To support 1.866GTS LPDDR4x timing script, need to add 233Mhz freq
to DDR PLL for second mission point at 933MTS. Otherwise DDR training
will fail.
Reviewed-by: Peng Fan <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
| -rw-r--r-- | arch/arm/mach-imx/imx9/clock.c | 1 | ||||
| -rw-r--r-- | drivers/ddr/imx/phy/ddrphy_utils.c | 4 |
2 files changed, 5 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c index 76d19f1cba3..12685f970de 100644 --- a/arch/arm/mach-imx/imx9/clock.c +++ b/arch/arm/mach-imx/imx9/clock.c @@ -41,6 +41,7 @@ static struct imx_fracpll_rate_table imx9_fracpll_tbl[] = { FRAC_PLL_RATE(466000000U, 1, 155, 8, 1, 3), /* 466Mhz */ FRAC_PLL_RATE(400000000U, 1, 200, 12, 0, 1), /* 400Mhz */ FRAC_PLL_RATE(300000000U, 1, 150, 12, 0, 1), + FRAC_PLL_RATE(233000000U, 1, 174, 18, 3, 4), /* 233Mhz */ }; /* return in khz */ diff --git a/drivers/ddr/imx/phy/ddrphy_utils.c b/drivers/ddr/imx/phy/ddrphy_utils.c index cf5bdad7abe..14278f5ad8f 100644 --- a/drivers/ddr/imx/phy/ddrphy_utils.c +++ b/drivers/ddr/imx/phy/ddrphy_utils.c @@ -148,6 +148,10 @@ void ddrphy_init_set_dfi_clk(unsigned int drate) dram_pll_init(MHZ(266)); dram_disable_bypass(); break; + case 933: + dram_pll_init(MHZ(233)); + dram_disable_bypass(); + break; case 667: dram_pll_init(MHZ(167)); dram_disable_bypass(); |