diff options
| author | Tingting Meng <[email protected]> | 2025-03-10 15:29:41 +0800 |
|---|---|---|
| committer | Tien Fong Chee <[email protected]> | 2025-04-22 11:47:40 +0800 |
| commit | 1f8d5085e985884ae1c82254d6e1af231f9d9e8b (patch) | |
| tree | de57a8d915b89f720629a5b9217421dec98a694a | |
| parent | 3d54b52addc0c8c58a7f9aa97c6c145d773a1e0e (diff) | |
arm: socfpga: agilex5: Add MMU mapping region
MMU mapping regions were added for the second and third DDR memory banks.
Signed-off-by: Tingting Meng <[email protected]>
| -rw-r--r-- | arch/arm/mach-socfpga/mmu-arm64_s10.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/mmu-arm64_s10.c b/arch/arm/mach-socfpga/mmu-arm64_s10.c index b8e40d9a788..1dc44ab4797 100644 --- a/arch/arm/mach-socfpga/mmu-arm64_s10.c +++ b/arch/arm/mach-socfpga/mmu-arm64_s10.c @@ -58,6 +58,20 @@ static struct mm_region socfpga_agilex5_mem_map[] = { .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE, }, { + /* MEM 30GB */ + .virt = 0x880000000UL, + .phys = 0x880000000UL, + .size = 0x780000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, { + /* MEM 480GB */ + .virt = 0x8800000000UL, + .phys = 0x8800000000UL, + .size = 0x7800000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE, + }, { /* List terminator */ }, }; |