diff options
| author | Rabeeh Khoury <[email protected]> | 2018-05-27 18:34:08 +0300 |
|---|---|---|
| committer | Stefan Roese <[email protected]> | 2018-06-05 07:25:42 +0200 |
| commit | 28be54dc59a038483650bd3c847b5444b371c2d0 (patch) | |
| tree | aa9c9ce8dbb85e56c044feef35a544082a005e2e | |
| parent | ee1855dc52fc366f33e21182103323c236cb3346 (diff) | |
mvebu: a38x: Force receiver detected on PCIe lanes
Some QCA988x based modules presence is not detected by the SERDES lanes,
so force this detection which will trigger the LTSSM state machine to
negotiate link.
An example of such a card is WLE900VX.
Signed-off-by: Rabeeh Khoury <[email protected]>
Signed-off-by: Baruch Siach <[email protected]>
Tested-by: Chris Packham <[email protected]>
Tested-by: Mario Six <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
| -rw-r--r-- | arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c | 2 | ||||
| -rw-r--r-- | arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index 13553cf9600..33e70569bc4 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -597,6 +597,8 @@ struct op_params pex_electrical_config_serdes_rev2_params[] = { {LANE_CFG4_REG, 0x800, 0x8, {0x8}, 0, 0}, /* tximpcal_th and rximpcal_th */ {VTHIMPCAL_CTRL_REG, 0x800, 0xff00, {0x3000}, 0, 0}, + /* Force receiver detected */ + {LANE_CFG0_REG, 0x800, 0x8000, {0x8000}, 0, 0}, }; /* PEX - configuration seq for REF_CLOCK_25MHz */ diff --git a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h index 953445b7d7a..50b23582665 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h +++ b/arch/arm/mach-mvebu/serdes/a38x/sys_env_lib.h @@ -71,6 +71,7 @@ #define RX_REG3 0xa0188 #define PCIE_REG1 0xa0288 #define PCIE_REG3 0xa0290 +#define LANE_CFG0_REG 0xa0600 #define LANE_CFG1_REG 0xa0604 #define LANE_CFG4_REG 0xa0620 #define LANE_CFG5_REG 0xa0624 |