Merge patch series "Update DDR Configurations"

Santhosh Kumar K <[email protected]> says:

This series is to update the DDR configurations of AM64x EVM, AM62x SK,
AM62x LP SK, AM62Ax SK and AM62Px SK boards according to the SysConfig
DDR Configuration tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02.

Test logs: https://gist.github.com/santhosh21/43723900f3615e4cf98da57ed9618cf9

Link: https://lore.kernel.org/r/[email protected]

5 files changed, 58 insertions, 50 deletions

diff --git a/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi b/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi
index c255ae6530f..ee9e213be84 100644
--- a/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi
+++ b/arch/arm/dts/k3-am62-lp4-50-800-800.dtsi
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.09.07
- * Wed Mar 01 2023 17:52:11 GMT-0600 (Central Standard Time)
+ * AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
+ * Tue Sep 17 2024 13:07:19 GMT+0530 (India Standard Time)
  * DDR Type: LPDDR4
  * F0 = 50MHz    F1 = NA     F2 = 800MHz
  * Density (per channel): 16Gb
@@ -13,6 +13,8 @@
 #define DDRSS_PLL_FHS_CNT 3
 #define DDRSS_PLL_FREQUENCY_1 400000000
 #define DDRSS_PLL_FREQUENCY_2 400000000
+#define DDRSS_SDRAM_IDX 15
+#define DDRSS_REGION_IDX 16
 
 #define DDRSS_CTL_0_DATA 0x00000B00
 #define DDRSS_CTL_1_DATA 0x00000000
@@ -847,7 +849,7 @@
 #define DDRSS_PHY_62_DATA 0x00000000
 #define DDRSS_PHY_63_DATA 0x00000000
 #define DDRSS_PHY_64_DATA 0x00000000
-#define DDRSS_PHY_65_DATA 0x00000004
+#define DDRSS_PHY_65_DATA 0x00000104
 #define DDRSS_PHY_66_DATA 0x00000000
 #define DDRSS_PHY_67_DATA 0x00000000
 #define DDRSS_PHY_68_DATA 0x00000000
@@ -869,7 +871,7 @@
 #define DDRSS_PHY_84_DATA 0x00100010
 #define DDRSS_PHY_85_DATA 0x00100010
 #define DDRSS_PHY_86_DATA 0x00100010
-#define DDRSS_PHY_87_DATA 0x02020010
+#define DDRSS_PHY_87_DATA 0x02000010
 #define DDRSS_PHY_88_DATA 0x51516041
 #define DDRSS_PHY_89_DATA 0x31C06000
 #define DDRSS_PHY_90_DATA 0x07AB0340
@@ -1103,7 +1105,7 @@
 #define DDRSS_PHY_318_DATA 0x00000000
 #define DDRSS_PHY_319_DATA 0x00000000
 #define DDRSS_PHY_320_DATA 0x00000000
-#define DDRSS_PHY_321_DATA 0x00000004
+#define DDRSS_PHY_321_DATA 0x00000104
 #define DDRSS_PHY_322_DATA 0x00000000
 #define DDRSS_PHY_323_DATA 0x00000000
 #define DDRSS_PHY_324_DATA 0x00000000
@@ -1125,7 +1127,7 @@
 #define DDRSS_PHY_340_DATA 0x00100010
 #define DDRSS_PHY_341_DATA 0x00100010
 #define DDRSS_PHY_342_DATA 0x00100010
-#define DDRSS_PHY_343_DATA 0x02020010
+#define DDRSS_PHY_343_DATA 0x02000010
 #define DDRSS_PHY_344_DATA 0x51516041
 #define DDRSS_PHY_345_DATA 0x31C06000
 #define DDRSS_PHY_346_DATA 0x07AB0340
@@ -2181,7 +2183,7 @@
 #define DDRSS_PHY_1396_DATA 0x0089FF00
 #define DDRSS_PHY_1397_DATA 0x000C3F11
 #define DDRSS_PHY_1398_DATA 0x01990000
-#define DDRSS_PHY_1399_DATA 0x000C3F11
+#define DDRSS_PHY_1399_DATA 0x000C3F91
 #define DDRSS_PHY_1400_DATA 0x01990000
 #define DDRSS_PHY_1401_DATA 0x3F0DFF11
 #define DDRSS_PHY_1402_DATA 0x01990000
diff --git a/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi b/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi
index 9f50d7eae69..35202651221 100644
--- a/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi
+++ b/arch/arm/dts/k3-am62a-ddr-1866mhz-32bit.dtsi
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM62A SysConfig DDR Subsystem Register Configuration Tool v0.09.01
- * Wed Aug 10 2022 17:34:54 GMT-0500 (Central Daylight Time)
+ * AM62Ax SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
+ * Tue Sep 17 2024 10:55:17 GMT+0530 (India Standard Time)
  * DDR Type: LPDDR4
  * F0 = 50MHz    F1 = NA     F2 = 1866MHz
  * Density (per channel): 8Gb
@@ -12,6 +12,8 @@
 #define DDRSS_PLL_FHS_CNT 5
 #define DDRSS_PLL_FREQUENCY_1 933000000
 #define DDRSS_PLL_FREQUENCY_2 933000000
+#define DDRSS_SDRAM_IDX 16
+#define DDRSS_REGION_IDX 17
 
 #define DDRSS_CTL_0_DATA 0x00000B00
 #define DDRSS_CTL_1_DATA 0x00000000
@@ -402,10 +404,10 @@
 #define DDRSS_CTL_386_DATA 0x01090903
 #define DDRSS_CTL_387_DATA 0x05020201
 #define DDRSS_CTL_388_DATA 0x0E081B1B
-#define DDRSS_CTL_389_DATA 0x0008030E
-#define DDRSS_CTL_390_DATA 0x0B12030E
-#define DDRSS_CTL_391_DATA 0x0B120314
-#define DDRSS_CTL_392_DATA 0x12120814
+#define DDRSS_CTL_389_DATA 0x0008040E
+#define DDRSS_CTL_390_DATA 0x0B120406
+#define DDRSS_CTL_391_DATA 0x0B120406
+#define DDRSS_CTL_392_DATA 0x12120806
 #define DDRSS_CTL_393_DATA 0x01000000
 #define DDRSS_CTL_394_DATA 0x07030701
 #define DDRSS_CTL_395_DATA 0x04000103
@@ -417,8 +419,8 @@
 #define DDRSS_CTL_401_DATA 0x00000200
 #define DDRSS_CTL_402_DATA 0x00000693
 #define DDRSS_CTL_403_DATA 0x00000E9C
-#define DDRSS_CTL_404_DATA 0x03050202
-#define DDRSS_CTL_405_DATA 0x37200201
+#define DDRSS_CTL_404_DATA 0x03000202
+#define DDRSS_CTL_405_DATA 0x37200404
 #define DDRSS_CTL_406_DATA 0x000038C8
 #define DDRSS_CTL_407_DATA 0x00000200
 #define DDRSS_CTL_408_DATA 0x00000200
@@ -426,8 +428,8 @@
 #define DDRSS_CTL_410_DATA 0x00000200
 #define DDRSS_CTL_411_DATA 0x0000FF84
 #define DDRSS_CTL_412_DATA 0x000237D0
-#define DDRSS_CTL_413_DATA 0x111F0402
-#define DDRSS_CTL_414_DATA 0x37200C0D
+#define DDRSS_CTL_413_DATA 0x111A0402
+#define DDRSS_CTL_414_DATA 0x37200C09
 #define DDRSS_CTL_415_DATA 0x000038C8
 #define DDRSS_CTL_416_DATA 0x00000200
 #define DDRSS_CTL_417_DATA 0x00000200
@@ -435,8 +437,8 @@
 #define DDRSS_CTL_419_DATA 0x00000200
 #define DDRSS_CTL_420_DATA 0x0000FF84
 #define DDRSS_CTL_421_DATA 0x000237D0
-#define DDRSS_CTL_422_DATA 0x111F0402
-#define DDRSS_CTL_423_DATA 0x00200C0D
+#define DDRSS_CTL_422_DATA 0x111A0402
+#define DDRSS_CTL_423_DATA 0x00200C09
 #define DDRSS_CTL_424_DATA 0x00000000
 #define DDRSS_CTL_425_DATA 0x02000A00
 #define DDRSS_CTL_426_DATA 0x00050003
@@ -939,7 +941,7 @@
 #define DDRSS_PHY_64_DATA 0x00000000
 #define DDRSS_PHY_65_DATA 0x00000000
 #define DDRSS_PHY_66_DATA 0x00000000
-#define DDRSS_PHY_67_DATA 0x00000004
+#define DDRSS_PHY_67_DATA 0x00000104
 #define DDRSS_PHY_68_DATA 0x00000000
 #define DDRSS_PHY_69_DATA 0x00000000
 #define DDRSS_PHY_70_DATA 0x00000000
@@ -964,7 +966,7 @@
 #define DDRSS_PHY_89_DATA 0x00100010
 #define DDRSS_PHY_90_DATA 0x00100010
 #define DDRSS_PHY_91_DATA 0x00100010
-#define DDRSS_PHY_92_DATA 0x02040010
+#define DDRSS_PHY_92_DATA 0x02000010
 #define DDRSS_PHY_93_DATA 0x00000005
 #define DDRSS_PHY_94_DATA 0x51516042
 #define DDRSS_PHY_95_DATA 0x31C06000
@@ -1195,7 +1197,7 @@
 #define DDRSS_PHY_320_DATA 0x00000000
 #define DDRSS_PHY_321_DATA 0x00000000
 #define DDRSS_PHY_322_DATA 0x00000000
-#define DDRSS_PHY_323_DATA 0x00000004
+#define DDRSS_PHY_323_DATA 0x00000104
 #define DDRSS_PHY_324_DATA 0x00000000
 #define DDRSS_PHY_325_DATA 0x00000000
 #define DDRSS_PHY_326_DATA 0x00000000
@@ -1220,7 +1222,7 @@
 #define DDRSS_PHY_345_DATA 0x00100010
 #define DDRSS_PHY_346_DATA 0x00100010
 #define DDRSS_PHY_347_DATA 0x00100010
-#define DDRSS_PHY_348_DATA 0x02040010
+#define DDRSS_PHY_348_DATA 0x02000010
 #define DDRSS_PHY_349_DATA 0x00000005
 #define DDRSS_PHY_350_DATA 0x51516042
 #define DDRSS_PHY_351_DATA 0x31C06000
@@ -1451,7 +1453,7 @@
 #define DDRSS_PHY_576_DATA 0x00000000
 #define DDRSS_PHY_577_DATA 0x00000000
 #define DDRSS_PHY_578_DATA 0x00000000
-#define DDRSS_PHY_579_DATA 0x00000004
+#define DDRSS_PHY_579_DATA 0x00000104
 #define DDRSS_PHY_580_DATA 0x00000000
 #define DDRSS_PHY_581_DATA 0x00000000
 #define DDRSS_PHY_582_DATA 0x00000000
@@ -1476,7 +1478,7 @@
 #define DDRSS_PHY_601_DATA 0x00100010
 #define DDRSS_PHY_602_DATA 0x00100010
 #define DDRSS_PHY_603_DATA 0x00100010
-#define DDRSS_PHY_604_DATA 0x02040010
+#define DDRSS_PHY_604_DATA 0x02000010
 #define DDRSS_PHY_605_DATA 0x00000005
 #define DDRSS_PHY_606_DATA 0x51516042
 #define DDRSS_PHY_607_DATA 0x31C06000
@@ -1707,7 +1709,7 @@
 #define DDRSS_PHY_832_DATA 0x00000000
 #define DDRSS_PHY_833_DATA 0x00000000
 #define DDRSS_PHY_834_DATA 0x00000000
-#define DDRSS_PHY_835_DATA 0x00000004
+#define DDRSS_PHY_835_DATA 0x00000104
 #define DDRSS_PHY_836_DATA 0x00000000
 #define DDRSS_PHY_837_DATA 0x00000000
 #define DDRSS_PHY_838_DATA 0x00000000
@@ -1732,7 +1734,7 @@
 #define DDRSS_PHY_857_DATA 0x00100010
 #define DDRSS_PHY_858_DATA 0x00100010
 #define DDRSS_PHY_859_DATA 0x00100010
-#define DDRSS_PHY_860_DATA 0x02040010
+#define DDRSS_PHY_860_DATA 0x02000010
 #define DDRSS_PHY_861_DATA 0x00000005
 #define DDRSS_PHY_862_DATA 0x51516042
 #define DDRSS_PHY_863_DATA 0x31C06000
@@ -2699,7 +2701,7 @@
 #define DDRSS_PHY_1824_DATA 0x0F0F0804
 #define DDRSS_PHY_1825_DATA 0x00800120
 #define DDRSS_PHY_1826_DATA 0x00041B42
-#define DDRSS_PHY_1827_DATA 0x00005201
+#define DDRSS_PHY_1827_DATA 0x00004201
 #define DDRSS_PHY_1828_DATA 0x00000000
 #define DDRSS_PHY_1829_DATA 0x00000000
 #define DDRSS_PHY_1830_DATA 0x00000000
@@ -2760,7 +2762,7 @@
 #define DDRSS_PHY_1885_DATA 0x00000002
 #define DDRSS_PHY_1886_DATA 0x00000000
 #define DDRSS_PHY_1887_DATA 0x00000000
-#define DDRSS_PHY_1888_DATA 0x00000AC4
+#define DDRSS_PHY_1888_DATA 0x0001F7C4
 #define DDRSS_PHY_1889_DATA 0x04000004
 #define DDRSS_PHY_1890_DATA 0x00000000
 #define DDRSS_PHY_1891_DATA 0x00001142
@@ -2789,10 +2791,10 @@
 #define DDRSS_PHY_1914_DATA 0x0089FF00
 #define DDRSS_PHY_1915_DATA 0x000C3F11
 #define DDRSS_PHY_1916_DATA 0x01990000
-#define DDRSS_PHY_1917_DATA 0x000C3F11
+#define DDRSS_PHY_1917_DATA 0x000C3F91
 #define DDRSS_PHY_1918_DATA 0x01990000
 #define DDRSS_PHY_1919_DATA 0x3F0DFF11
 #define DDRSS_PHY_1920_DATA 0x00EF0000
 #define DDRSS_PHY_1921_DATA 0x00018011
 #define DDRSS_PHY_1922_DATA 0x0089FF00
-#define DDRSS_PHY_1923_DATA 0x20040004
+#define DDRSS_PHY_1923_DATA 0x20040006
diff --git a/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi b/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi
index f6643520153..c7e33ba50b9 100644
--- a/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi
+++ b/arch/arm/dts/k3-am62p-ddr-lp4-50-1600.dtsi
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM62Px SysConfig DDR Subsystem Register Configuration Tool v0.10.02
- * Thu Jan 25 2024 10:43:46 GMT-0600 (Central Standard Time)
+ * AM62Px SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
+ * Tue Sep 17 2024 11:03:07 GMT+0530 (India Standard Time)
  * DDR Type: LPDDR4
  * F0 = 50MHz    F1 = NA     F2 = 1600MHz
  * Density (per channel): 16Gb
@@ -941,7 +941,7 @@
 #define DDRSS_PHY_64_DATA 0x00000000
 #define DDRSS_PHY_65_DATA 0x00000000
 #define DDRSS_PHY_66_DATA 0x00000000
-#define DDRSS_PHY_67_DATA 0x00000004
+#define DDRSS_PHY_67_DATA 0x00000104
 #define DDRSS_PHY_68_DATA 0x00000000
 #define DDRSS_PHY_69_DATA 0x00000000
 #define DDRSS_PHY_70_DATA 0x00000000
@@ -1197,7 +1197,7 @@
 #define DDRSS_PHY_320_DATA 0x00000000
 #define DDRSS_PHY_321_DATA 0x00000000
 #define DDRSS_PHY_322_DATA 0x00000000
-#define DDRSS_PHY_323_DATA 0x00000004
+#define DDRSS_PHY_323_DATA 0x00000104
 #define DDRSS_PHY_324_DATA 0x00000000
 #define DDRSS_PHY_325_DATA 0x00000000
 #define DDRSS_PHY_326_DATA 0x00000000
@@ -1453,7 +1453,7 @@
 #define DDRSS_PHY_576_DATA 0x00000000
 #define DDRSS_PHY_577_DATA 0x00000000
 #define DDRSS_PHY_578_DATA 0x00000000
-#define DDRSS_PHY_579_DATA 0x00000004
+#define DDRSS_PHY_579_DATA 0x00000104
 #define DDRSS_PHY_580_DATA 0x00000000
 #define DDRSS_PHY_581_DATA 0x00000000
 #define DDRSS_PHY_582_DATA 0x00000000
@@ -1709,7 +1709,7 @@
 #define DDRSS_PHY_832_DATA 0x00000000
 #define DDRSS_PHY_833_DATA 0x00000000
 #define DDRSS_PHY_834_DATA 0x00000000
-#define DDRSS_PHY_835_DATA 0x00000004
+#define DDRSS_PHY_835_DATA 0x00000104
 #define DDRSS_PHY_836_DATA 0x00000000
 #define DDRSS_PHY_837_DATA 0x00000000
 #define DDRSS_PHY_838_DATA 0x00000000
diff --git a/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi
index d92e3ce048b..8def52b07f4 100644
--- a/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi
+++ b/arch/arm/dts/k3-am62x-sk-ddr4-1600MTs.dtsi
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM62x SysConfig DDR Subsystem Register Configuration Tool v0.08.60
- * Wed Mar 16 2022 17:41:20 GMT-0500 (Central Daylight Time)
+ * AM623/AM625 SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
+ * Tue Sep 17 2024 11:00:17 GMT+0530 (India Standard Time)
  * DDR Type: DDR4
  * Frequency = 800MHz (1600MTs)
  * Density: 16Gb
@@ -12,6 +12,8 @@
 #define DDRSS_PLL_FHS_CNT 6
 #define DDRSS_PLL_FREQUENCY_1 400000000
 #define DDRSS_PLL_FREQUENCY_2 400000000
+#define DDRSS_SDRAM_IDX 15
+#define DDRSS_REGION_IDX 17
 
 #define DDRSS_CTL_0_DATA 0x00000A00
 #define DDRSS_CTL_1_DATA 0x00000000
@@ -334,7 +336,7 @@
 #define DDRSS_CTL_318_DATA 0x3FFF0000
 #define DDRSS_CTL_319_DATA 0x000FFF00
 #define DDRSS_CTL_320_DATA 0xFFFFFFFF
-#define DDRSS_CTL_321_DATA 0x000FFF00
+#define DDRSS_CTL_321_DATA 0x00FFFF00
 #define DDRSS_CTL_322_DATA 0x0A000000
 #define DDRSS_CTL_323_DATA 0x0001FFFF
 #define DDRSS_CTL_324_DATA 0x01010101
@@ -901,7 +903,7 @@
 #define DDRSS_PHY_117_DATA 0x00800080
 #define DDRSS_PHY_118_DATA 0x00800080
 #define DDRSS_PHY_119_DATA 0x01000080
-#define DDRSS_PHY_120_DATA 0x01A00000
+#define DDRSS_PHY_120_DATA 0x01000000
 #define DDRSS_PHY_121_DATA 0x00000000
 #define DDRSS_PHY_122_DATA 0x00000000
 #define DDRSS_PHY_123_DATA 0x00080200
@@ -1157,7 +1159,7 @@
 #define DDRSS_PHY_373_DATA 0x00800080
 #define DDRSS_PHY_374_DATA 0x00800080
 #define DDRSS_PHY_375_DATA 0x01000080
-#define DDRSS_PHY_376_DATA 0x01A00000
+#define DDRSS_PHY_376_DATA 0x01000000
 #define DDRSS_PHY_377_DATA 0x00000000
 #define DDRSS_PHY_378_DATA 0x00000000
 #define DDRSS_PHY_379_DATA 0x00080200
@@ -2152,7 +2154,7 @@
 #define DDRSS_PHY_1368_DATA 0x00000002
 #define DDRSS_PHY_1369_DATA 0x00000100
 #define DDRSS_PHY_1370_DATA 0x00000000
-#define DDRSS_PHY_1371_DATA 0x0001F7C0
+#define DDRSS_PHY_1371_DATA 0x0001F7C2
 #define DDRSS_PHY_1372_DATA 0x00020002
 #define DDRSS_PHY_1373_DATA 0x00000000
 #define DDRSS_PHY_1374_DATA 0x00001142
diff --git a/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi b/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi
index 491412119b1..1b5fabc3dd1 100644
--- a/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi
+++ b/arch/arm/dts/k3-am64-evm-ddr4-1600MTs.dtsi
@@ -1,8 +1,8 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * This file was generated with the
- * AM64x SysConfig DDR Subsystem Register Configuration Tool v0.08.40
- * Wed Feb 02 2022 16:24:50 GMT-0600 (Central Standard Time)
+ * AM64x SysConfig DDR Configuration Tool for AM64x, AM625, AM623, AM62Ax, AM62Px v0.10.02
+ * Tue Sep 17 2024 11:01:31 GMT+0530 (India Standard Time)
  * DDR Type: DDR4
  * Frequency = 800MHz (1600MTs)
  * Density: 16Gb
@@ -12,6 +12,8 @@
 #define DDRSS_PLL_FHS_CNT 6
 #define DDRSS_PLL_FREQUENCY_1 400000000
 #define DDRSS_PLL_FREQUENCY_2 400000000
+#define DDRSS_SDRAM_IDX 15
+#define DDRSS_REGION_IDX 15
 
 #define DDRSS_CTL_0_DATA 0x00000A00
 #define DDRSS_CTL_1_DATA 0x00000000
@@ -178,7 +180,7 @@
 #define DDRSS_CTL_162_DATA 0x0E0A0907
 #define DDRSS_CTL_163_DATA 0x0A090000
 #define DDRSS_CTL_164_DATA 0x0A090701
-#define DDRSS_CTL_165_DATA 0x0000000E
+#define DDRSS_CTL_165_DATA 0x0000080E
 #define DDRSS_CTL_166_DATA 0x00040003
 #define DDRSS_CTL_167_DATA 0x00000007
 #define DDRSS_CTL_168_DATA 0x00000000
@@ -334,7 +336,7 @@
 #define DDRSS_CTL_318_DATA 0x3FFF0000
 #define DDRSS_CTL_319_DATA 0x000FFF00
 #define DDRSS_CTL_320_DATA 0xFFFFFFFF
-#define DDRSS_CTL_321_DATA 0x000FFF00
+#define DDRSS_CTL_321_DATA 0x00FFFF00
 #define DDRSS_CTL_322_DATA 0x0A000000
 #define DDRSS_CTL_323_DATA 0x0001FFFF
 #define DDRSS_CTL_324_DATA 0x01010101
@@ -901,7 +903,7 @@
 #define DDRSS_PHY_117_DATA 0x00800080
 #define DDRSS_PHY_118_DATA 0x00800080
 #define DDRSS_PHY_119_DATA 0x01000080
-#define DDRSS_PHY_120_DATA 0x01A00000
+#define DDRSS_PHY_120_DATA 0x01000000
 #define DDRSS_PHY_121_DATA 0x00000000
 #define DDRSS_PHY_122_DATA 0x00000000
 #define DDRSS_PHY_123_DATA 0x00080200
@@ -1157,7 +1159,7 @@
 #define DDRSS_PHY_373_DATA 0x00800080
 #define DDRSS_PHY_374_DATA 0x00800080
 #define DDRSS_PHY_375_DATA 0x01000080
-#define DDRSS_PHY_376_DATA 0x01A00000
+#define DDRSS_PHY_376_DATA 0x01000000
 #define DDRSS_PHY_377_DATA 0x00000000
 #define DDRSS_PHY_378_DATA 0x00000000
 #define DDRSS_PHY_379_DATA 0x00080200
@@ -2152,7 +2154,7 @@
 #define DDRSS_PHY_1368_DATA 0x00000002
 #define DDRSS_PHY_1369_DATA 0x00000100
 #define DDRSS_PHY_1370_DATA 0x00000000
-#define DDRSS_PHY_1371_DATA 0x0001F7C0
+#define DDRSS_PHY_1371_DATA 0x0001F7C2
 #define DDRSS_PHY_1372_DATA 0x00020002
 #define DDRSS_PHY_1373_DATA 0x00000000
 #define DDRSS_PHY_1374_DATA 0x00001142