diff options
| author | Marek Vasut <[email protected]> | 2022-01-25 03:48:06 +0100 |
|---|---|---|
| committer | Stefano Babic <[email protected]> | 2022-02-05 15:49:01 +0100 |
| commit | 2c9d2acefaae8ae6d68d496b33a4dfa559006273 (patch) | |
| tree | 8e875acb06b53ba88421a3bee2708ab764f2958a | |
| parent | 66e90be99fcdb4dc1d01ca7dfa6ca3de58b5bbc0 (diff) | |
ARM: imx: imx8m: Add PLL 1.4 GHz, 1.5 GHz, 1.6 GHz, 1.8 GHz options
Add PLL 1.4 GHz, 1.5 GHz, 1.6 GHz, 1.8 GHz options for iMX8M SoCs
in case they should be operated faster, e.g. to improve boot time.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Peng Fan <[email protected]>
Cc: Stefano Babic <[email protected]>
| -rw-r--r-- | arch/arm/mach-imx/imx8m/clock_imx8mm.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx8m/clock_imx8mm.c b/arch/arm/mach-imx/imx8m/clock_imx8mm.c index 2ca3bf68e74..76132defc21 100644 --- a/arch/arm/mach-imx/imx8m/clock_imx8mm.c +++ b/arch/arm/mach-imx/imx8m/clock_imx8mm.c @@ -248,6 +248,26 @@ int intpll_configure(enum pll_clocks pll, ulong freq) pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x12c) | INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1); break; + case MHZ(1400): + /* 24 * 0x15e / 3 / 2 ^ 1 */ + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x15e) | + INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1); + break; + case MHZ(1500): + /* 24 * 0x177 / 3 / 2 ^ 1 */ + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0x177) | + INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(1); + break; + case MHZ(1600): + /* 24 * 0xc8 / 3 / 2 ^ 0 */ + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xc8) | + INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0); + break; + case MHZ(1800): + /* 24 * 0xe1 / 3 / 2 ^ 0 */ + pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xe1) | + INTPLL_PRE_DIV_VAL(3) | INTPLL_POST_DIV_VAL(0); + break; case MHZ(2000): /* 24 * 0xfa / 3 / 2 ^ 0 */ pll_div_ctl_val = INTPLL_MAIN_DIV_VAL(0xfa) | |