diff options
| author | Mayuresh Chitale <[email protected]> | 2025-05-29 03:30:51 +0000 |
|---|---|---|
| committer | Leo Yu-Chi Liang <[email protected]> | 2025-06-02 16:18:33 +0800 |
| commit | 31e215fde81417299e45a6ae4a7ee880fac84c37 (patch) | |
| tree | 50ed54a1c2d4c2390ca16d5315f17637b19bdaf7 | |
| parent | 29a2025d77192e510580403b793ae027af19c81c (diff) | |
Revert "riscv: image: Add new image type for RV64"
This reverts commit 14a4792a71db3561bea065415ac1f2ac69ef32b5 as
discussed in [1].
[1] https://lists.denx.de/pipermail/u-boot/2025-May/590841.html
Signed-off-by: Mayuresh Chitale <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
| -rw-r--r-- | boot/image.c | 3 | ||||
| -rw-r--r-- | include/image.h | 3 |
2 files changed, 2 insertions, 4 deletions
diff --git a/boot/image.c b/boot/image.c index 45299a7dc33..139c5bd035a 100644 --- a/boot/image.c +++ b/boot/image.c @@ -92,8 +92,7 @@ static const table_entry_t uimage_arch[] = { { IH_ARCH_ARC, "arc", "ARC", }, { IH_ARCH_X86_64, "x86_64", "AMD x86_64", }, { IH_ARCH_XTENSA, "xtensa", "Xtensa", }, - { IH_ARCH_RISCV, "riscv", "RISC-V 32 Bit",}, - { IH_ARCH_RISCV64, "riscv64", "RISC-V 64 Bit",}, + { IH_ARCH_RISCV, "riscv", "RISC-V", }, { -1, "", "", }, }; diff --git a/include/image.h b/include/image.h index 4620782c069..c1db8383459 100644 --- a/include/image.h +++ b/include/image.h @@ -138,8 +138,7 @@ enum { IH_ARCH_ARC, /* Synopsys DesignWare ARC */ IH_ARCH_X86_64, /* AMD x86_64, Intel and Via */ IH_ARCH_XTENSA, /* Xtensa */ - IH_ARCH_RISCV, /* RISC-V 32 bit*/ - IH_ARCH_RISCV64, /* RISC-V 64 bit*/ + IH_ARCH_RISCV, /* RISC-V */ IH_ARCH_COUNT, }; |