clk: mediatek: mt7988: deduplicate clock gate drivers

MT7988 declares a separate U_BOOT_DRIVER, probe() function and compatible
table for each clock gate controller, despite all of them sharing the same
implementation.

Describe the gates directly in each controller's struct mtk_clk_tree,
reference the trees from the driver data and use the generic
mtk_clk_topckgen_ops. The two sgmiisys controllers, which share the same DM
flags and (absent) bind() callback, are merged into a single U_BOOT_DRIVER;
ethdma and ethwarp keep their own drivers since they bind reset controllers
at different offsets.

This also stops using mtk_common_clk_gate_init() and struct mtk_cg_priv,
which are scheduled for removal.

No functional change intended.

Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-15-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>

1 files changed, 49 insertions, 55 deletions

diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index ebad78a9151..6637ab4c287 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -838,10 +838,12 @@ static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {
 	.type = MTK_CLK_TREE_INFRASYS,
 };
 
-static const struct mtk_clk_tree mt7988_clk_tree = {
-	.ext_clk_rates = ext_clock_rates,
-	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
-};
+static int mt7988_clk_probe(struct udevice *dev)
+{
+	const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
+
+	return mtk_common_clk_init(dev, tree);
+}
 
 static const struct udevice_id mt7988_fixed_pll_compat[] = {
 	{ .compatible = "mediatek,mt7988-fixed-plls" },
@@ -933,11 +935,12 @@ static const struct mtk_gate ethdma_mtk_gate[] = {
 	GATE_ETHDMA(CLK_ETHDMA_FE_EN, "ethdma_fe_en", CLK_TOP_NETSYS_2X_SEL, 6),
 };
 
-static int mt7988_ethdma_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7988_clk_tree, ethdma_mtk_gate,
-					ARRAY_SIZE(ethdma_mtk_gate), 0);
-}
+static const struct mtk_clk_tree mt7988_ethdma_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = ethdma_mtk_gate,
+	.num_gates = ARRAY_SIZE(ethdma_mtk_gate),
+};
 
 static int mt7988_ethdma_bind(struct udevice *dev)
 {
@@ -955,6 +958,7 @@ static int mt7988_ethdma_bind(struct udevice *dev)
 static const struct udevice_id mt7988_ethdma_compat[] = {
 	{
 		.compatible = "mediatek,mt7988-ethdma",
+		.data = (ulong)&mt7988_ethdma_clk_tree,
 	},
 	{}
 };
@@ -963,10 +967,10 @@ U_BOOT_DRIVER(mt7988_clk_ethdma) = {
 	.name = "mt7988-clock-ethdma",
 	.id = UCLASS_CLK,
 	.of_match = mt7988_ethdma_compat,
-	.probe = mt7988_ethdma_probe,
+	.probe = mt7988_clk_probe,
 	.bind = mt7988_ethdma_bind,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 };
 
 /* SGMIISYS_0 */
@@ -991,27 +995,11 @@ static const struct mtk_gate sgmiisys_0_mtk_gate[] = {
 	GATE_SGMII0(CLK_SGM0_RX_EN, "sgm0_rx_en", CLK_TOP_XTAL, 3),
 };
 
-static int mt7988_sgmiisys_0_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7988_clk_tree,
-					sgmiisys_0_mtk_gate,
-					ARRAY_SIZE(sgmiisys_0_mtk_gate), 0);
-}
-
-static const struct udevice_id mt7988_sgmiisys_0_compat[] = {
-	{
-		.compatible = "mediatek,mt7988-sgmiisys_0",
-	},
-	{}
-};
-
-U_BOOT_DRIVER(mt7988_clk_sgmiisys_0) = {
-	.name = "mt7988-clock-sgmiisys_0",
-	.id = UCLASS_CLK,
-	.of_match = mt7988_sgmiisys_0_compat,
-	.probe = mt7988_sgmiisys_0_probe,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+static const struct mtk_clk_tree mt7988_sgmiisys_0_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = sgmiisys_0_mtk_gate,
+	.num_gates = ARRAY_SIZE(sgmiisys_0_mtk_gate),
 };
 
 /* SGMIISYS_1 */
@@ -1036,27 +1024,32 @@ static const struct mtk_gate sgmiisys_1_mtk_gate[] = {
 	GATE_SGMII1(CLK_SGM1_RX_EN, "sgm1_rx_en", CLK_TOP_XTAL, 3),
 };
 
-static int mt7988_sgmiisys_1_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7988_clk_tree,
-					sgmiisys_1_mtk_gate,
-					ARRAY_SIZE(sgmiisys_1_mtk_gate), 0);
-}
+static const struct mtk_clk_tree mt7988_sgmiisys_1_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = sgmiisys_1_mtk_gate,
+	.num_gates = ARRAY_SIZE(sgmiisys_1_mtk_gate),
+};
 
-static const struct udevice_id mt7988_sgmiisys_1_compat[] = {
+static const struct udevice_id of_match_mt7988_sgmiisys[] = {
+	{
+		.compatible = "mediatek,mt7988-sgmiisys_0",
+		.data = (ulong)&mt7988_sgmiisys_0_clk_tree,
+	},
 	{
 		.compatible = "mediatek,mt7988-sgmiisys_1",
+		.data = (ulong)&mt7988_sgmiisys_1_clk_tree,
 	},
 	{}
 };
 
-U_BOOT_DRIVER(mt7988_clk_sgmiisys_1) = {
-	.name = "mt7988-clock-sgmiisys_1",
+U_BOOT_DRIVER(mt7988_clk_sgmiisys) = {
+	.name = "mt7988-clock-sgmiisys",
 	.id = UCLASS_CLK,
-	.of_match = mt7988_sgmiisys_1_compat,
-	.probe = mt7988_sgmiisys_1_probe,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.of_match = of_match_mt7988_sgmiisys,
+	.probe = mt7988_clk_probe,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 };
 
 /* ETHWARP */
@@ -1083,12 +1076,12 @@ static const struct mtk_gate ethwarp_mtk_gate[] = {
 		     CLK_TOP_NETSYS_MCU_SEL, 15),
 };
 
-static int mt7988_ethwarp_probe(struct udevice *dev)
-{
-	return mtk_common_clk_gate_init(dev, &mt7988_clk_tree,
-					ethwarp_mtk_gate,
-					ARRAY_SIZE(ethwarp_mtk_gate), 0);
-}
+static const struct mtk_clk_tree mt7988_ethwarp_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.gates = ethwarp_mtk_gate,
+	.num_gates = ARRAY_SIZE(ethwarp_mtk_gate),
+};
 
 static int mt7988_ethwarp_bind(struct udevice *dev)
 {
@@ -1106,6 +1099,7 @@ static int mt7988_ethwarp_bind(struct udevice *dev)
 static const struct udevice_id mt7988_ethwarp_compat[] = {
 	{
 		.compatible = "mediatek,mt7988-ethwarp",
+		.data = (ulong)&mt7988_ethwarp_clk_tree,
 	},
 	{}
 };
@@ -1114,8 +1108,8 @@ U_BOOT_DRIVER(mt7988_clk_ethwarp) = {
 	.name = "mt7988-clock-ethwarp",
 	.id = UCLASS_CLK,
 	.of_match = mt7988_ethwarp_compat,
-	.probe = mt7988_ethwarp_probe,
+	.probe = mt7988_clk_probe,
 	.bind = mt7988_ethwarp_bind,
-	.priv_auto = sizeof(struct mtk_cg_priv),
-	.ops = &mtk_clk_gate_ops,
+	.priv_auto = sizeof(struct mtk_clk_priv),
+	.ops = &mtk_clk_topckgen_ops,
 };