diff options
| author | David Lechner <[email protected]> | 2026-07-10 13:56:24 -0500 |
|---|---|---|
| committer | David Lechner <[email protected]> | 2026-07-22 12:01:17 -0500 |
| commit | 3bb8ad2397cd4f84472fafdbb3d557320a5ac8a0 (patch) | |
| tree | 13f45b9cb5b32fe78835bbd13db6d4845e4544ba | |
| parent | de2cffba44c066c4b38d9e8c412060258b50afa8 (diff) | |
clk: mediaTek: mt7987: add clock tree type flags
Add clock tree type flags to the mt7987 clock tree structures. These
will be used later for parent lookup.
Link: https://patch.msgid.link/20260710-mtk-clk-parent-lookup-improvements-v2-8-f3f3a4a28dca@baylibre.com
Signed-off-by: David Lechner <[email protected]>
| -rw-r--r-- | drivers/clk/mediatek/clk-mt7987.c | 13 |
1 files changed, 12 insertions, 1 deletions
diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c index 5f102636079..27367de82ff 100644 --- a/drivers/clk/mediatek/clk-mt7987.c +++ b/drivers/clk/mediatek/clk-mt7987.c @@ -60,6 +60,7 @@ static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = { .fclks = apmixedsys_mtk_plls, .num_fclks = ARRAY_SIZE(apmixedsys_mtk_plls), .flags = CLK_PARENT_APMIXED, + .type = MTK_CLK_TREE_APMIXED, }; static const struct udevice_id mt7987_fixed_pll_compat[] = { @@ -77,6 +78,7 @@ U_BOOT_DRIVER(mtk_clk_apmixedsys) = { .name = "mt7987-clock-fixed-pll", .id = UCLASS_CLK, .of_match = mt7987_fixed_pll_compat, + .bind = mtk_common_clk_parent_bind, .probe = mt7987_fixed_pll_probe, .priv_auto = sizeof(struct mtk_clk_priv), .ops = &mtk_clk_fixed_pll_ops, @@ -457,6 +459,12 @@ static const struct mtk_clk_tree mt7987_topckgen_clk_tree = { .num_fdivs = ARRAY_SIZE(topckgen_mtk_fixed_factors), .num_muxes = ARRAY_SIZE(topckgen_mtk_muxes), .flags = CLK_PARENT_TOPCKGEN, + .type = MTK_CLK_TREE_TOPCKGEN, +}; + +static const struct mtk_clk_tree mt7987_clk_tree = { + .ext_clk_rates = ext_clock_rates, + .num_ext_clks = ARRAY_SIZE(ext_clock_rates), }; static const struct udevice_id mt7987_topckgen_compat[] = { @@ -480,6 +488,7 @@ U_BOOT_DRIVER(mtk_clk_topckgen) = { .name = "mt7987-clock-topckgen", .id = UCLASS_CLK, .of_match = mt7987_topckgen_compat, + .bind = mtk_common_clk_parent_bind, .probe = mt7987_topckgen_probe, .priv_auto = sizeof(struct mtk_clk_priv), .ops = &mtk_clk_topckgen_ops, @@ -783,6 +792,7 @@ static const struct mtk_clk_tree mt7987_infracfg_clk_tree = { .gates = infracfg_mtk_gates, .num_muxes = ARRAY_SIZE(infracfg_mtk_mux), .num_gates = ARRAY_SIZE(infracfg_mtk_gates), + .type = MTK_CLK_TREE_INFRASYS, }; static const struct udevice_id mt7987_infracfg_compat[] = { @@ -800,6 +810,7 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = { .name = "mt7987-clock-infracfg", .id = UCLASS_CLK, .of_match = mt7987_infracfg_compat, + .bind = mtk_common_clk_parent_bind, .probe = mt7987_infracfg_probe, .priv_auto = sizeof(struct mtk_clk_priv), .ops = &mtk_clk_infrasys_ops, @@ -829,7 +840,7 @@ static const struct mtk_gate eth_cgs[] = { static int mt7987_ethsys_probe(struct udevice *dev) { - return mtk_common_clk_gate_init(dev, &mt7987_topckgen_clk_tree, eth_cgs, + return mtk_common_clk_gate_init(dev, &mt7987_clk_tree, eth_cgs, ARRAY_SIZE(eth_cgs), 0); } |