diff options
| author | Zong Li <[email protected]> | 2023-12-14 14:09:37 +0000 |
|---|---|---|
| committer | Leo Yu-Chi Liang <[email protected]> | 2023-12-27 17:28:57 +0800 |
| commit | 40c76dfed29ac2173bd32d730979ef2531029048 (patch) | |
| tree | e481fe5e4eed432724f4891497b7c026cef938ec | |
| parent | 64e8482f1c94ab6e1fb4837a8744ca8a156c507e (diff) | |
riscv: cache: support cache enable in SPL stage
The power gating feature of pl2 should be enabled as early as possible,
it would be better to put it in SPL stage.
Signed-off-by: Zong Li <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
| -rw-r--r-- | arch/riscv/lib/sifive_cache.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/arch/riscv/lib/sifive_cache.c b/arch/riscv/lib/sifive_cache.c index 39b0248c323..d8fe1dfa958 100644 --- a/arch/riscv/lib/sifive_cache.c +++ b/arch/riscv/lib/sifive_cache.c @@ -7,7 +7,10 @@ #include <cpu_func.h> #include <log.h> #include <dm.h> +#include <dm/device-internal.h> +#include <dm/uclass-internal.h> +#ifndef CONFIG_SPL_BUILD void enable_caches(void) { struct udevice *dev; @@ -25,3 +28,21 @@ void enable_caches(void) log_debug("ccache enable failed"); } } +#else +static inline void probe_cache_device(struct driver *driver, struct udevice *dev) +{ + for (uclass_find_first_device(UCLASS_CACHE, &dev); + dev; + uclass_find_next_device(&dev)) { + if (dev->driver == driver) + device_probe(dev); + } +} + +void enable_caches(void) +{ + struct udevice *dev = NULL; + + probe_cache_device(DM_DRIVER_GET(sifive_pl2), dev); +} +#endif /* !CONFIG_SPL_BUILD */ |