diff options
| author | Timur Tabi <[email protected]> | 2011-10-31 13:30:43 -0500 |
|---|---|---|
| committer | Kumar Gala <[email protected]> | 2011-11-08 08:31:02 -0600 |
| commit | 452ad61c3feeffbf2b5ff74f0a6797af3ba4882c (patch) | |
| tree | 62d4ea07003a0c2576467731a4e14e025a66c385 | |
| parent | c2efa0aa1e484448d553b37df9738095b113a71c (diff) | |
powerpc/85xx: add some missing sync instructions in the CCSR relocation code
Calls to tlbwe and tlbsx should be preceded with an isync/msync pair.
Signed-off-by: Timur Tabi <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 275accca5b9..e519f35d9a1 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -352,6 +352,8 @@ purge_old_ccsr_tlb: li r1, 0 mtspr MAS6, r1 /* Search the current address space and PID */ + isync + msync tlbsx 0, r8 mfspr r1, MAS1 andis. r2, r1, MAS1_VALID@h /* Check for the Valid bit */ @@ -359,6 +361,8 @@ purge_old_ccsr_tlb: rlwinm r1, r1, 0, 1, 31 /* Clear Valid bit */ mtspr MAS1, r1 + isync + msync tlbwe 1: |