diff options
| author | Kumar Gala <[email protected]> | 2011-01-05 10:33:46 -0600 |
|---|---|---|
| committer | Kumar Gala <[email protected]> | 2011-01-14 01:32:19 -0600 |
| commit | 45a68135c12bf7d534f3ce25bef493e16d32cedb (patch) | |
| tree | 27ab291ad3028123a63417df4997bab1e1bce19a | |
| parent | 7ea3871e06c421a44e7286792610dc00992070e6 (diff) | |
powerpc/85xx: Fix bug in dcache_disable
We set the L1 dache register with a bogus register value. Need to be
using 'r3' instead of 'r0'.
Reported-by: John Traill <[email protected]>
Signed-off-by: Kumar Gala <[email protected]>
| -rw-r--r-- | arch/powerpc/cpu/mpc85xx/start.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 945c1b84779..fa98af64b54 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -1,5 +1,5 @@ /* - * Copyright 2004, 2007-2010 Freescale Semiconductor, Inc. + * Copyright 2004, 2007-2011 Freescale Semiconductor, Inc. * Copyright (C) 2003 Motorola,Inc. * * See file CREDITS for list of people who contributed to this @@ -753,7 +753,7 @@ dcache_disable: lis r4,0 ori r4,r4,L1CSR0_DCE andc r3,r3,r4 - mtspr L1CSR0,r0 + mtspr L1CSR0,r3 isync blr |