summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorJulien Stephan <[email protected]>2026-07-15 16:28:34 +0200
committerDavid Lechner <[email protected]>2026-07-29 10:04:25 -0500
commit45c29eade55b30be4a3bfe1907308d62322bd574 (patch)
tree1a766f31bea9bae4c64f13f3485ce9469fb923d2
parent2428c2b14182f08d1ae1cafc2b76cddf8a5b9355 (diff)
clk: mediatek: mt7623: use driver data to store the clock tree
Pass each controller's struct mtk_clk_tree through the driver data and use the generic probe function for all the MT7623 clock drivers, instead of a dedicated probe per controller. The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since they rely on dedicated ops and on the parent bind() callback, but they now get their tree from the compatible data. The apmixedsys probe still performs its SoC specific register tweaks. No functional change intended. Signed-off-by: Julien Stephan <[email protected]> Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-6-23e907516010@baylibre.com Signed-off-by: David Lechner <[email protected]>
-rw-r--r--drivers/clk/mediatek/clk-mt7623.c32
1 files changed, 16 insertions, 16 deletions
diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
index 1b8507eb8ef..6a6e61af5db 100644
--- a/drivers/clk/mediatek/clk-mt7623.c
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -1045,9 +1045,10 @@ static int mt7623_mcucfg_probe(struct udevice *dev)
static int mt7623_apmixedsys_probe(struct udevice *dev)
{
struct mtk_clk_priv *priv = dev_get_priv(dev);
+ const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev);
int ret;
- ret = mtk_common_clk_init(dev, &mt7623_apmixedsys_clk_tree);
+ ret = mtk_common_clk_init(dev, tree);
if (ret)
return ret;
@@ -1059,11 +1060,6 @@ static int mt7623_apmixedsys_probe(struct udevice *dev)
return 0;
}
-static int mt7623_topckgen_probe(struct udevice *dev)
-{
- return mtk_common_clk_init(dev, &mt7623_topckgen_clk_tree);
-}
-
static const struct mtk_clk_tree mt7623_infracfg_tree = {
.ext_clk_rates = ext_clock_rates,
.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
@@ -1108,11 +1104,6 @@ static const struct mtk_clk_tree mt7623_clk_peri_tree = {
.num_gates = ARRAY_SIZE(peri_cgs),
};
-static int mt7623_pericfg_probe(struct udevice *dev)
-{
- return mtk_common_clk_init(dev, &mt7623_clk_peri_tree);
-}
-
static int mt7623_ethsys_hifsys_bind(struct udevice *dev)
{
int ret = 0;
@@ -1127,12 +1118,18 @@ static int mt7623_ethsys_hifsys_bind(struct udevice *dev)
}
static const struct udevice_id mt7623_apmixed_compat[] = {
- { .compatible = "mediatek,mt7623-apmixedsys" },
+ {
+ .compatible = "mediatek,mt7623-apmixedsys",
+ .data = (ulong)&mt7623_apmixedsys_clk_tree,
+ },
{ }
};
static const struct udevice_id mt7623_topckgen_compat[] = {
- { .compatible = "mediatek,mt7623-topckgen" },
+ {
+ .compatible = "mediatek,mt7623-topckgen",
+ .data = (ulong)&mt7623_topckgen_clk_tree,
+ },
{ }
};
@@ -1145,7 +1142,10 @@ static const struct udevice_id mt7623_infracfg_compat[] = {
};
static const struct udevice_id mt7623_pericfg_compat[] = {
- { .compatible = "mediatek,mt7623-pericfg", },
+ {
+ .compatible = "mediatek,mt7623-pericfg",
+ .data = (ulong)&mt7623_clk_peri_tree,
+ },
{ }
};
@@ -1190,7 +1190,7 @@ U_BOOT_DRIVER(mt7623_clk_topckgen) = {
.id = UCLASS_CLK,
.of_match = mt7623_topckgen_compat,
.bind = mtk_common_clk_parent_bind,
- .probe = mt7623_topckgen_probe,
+ .probe = mt7623_clk_probe,
.priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_topckgen_ops,
.flags = DM_FLAG_PRE_RELOC,
@@ -1210,7 +1210,7 @@ U_BOOT_DRIVER(mt7623_clk_pericfg) = {
.name = "mt7623-pericfg",
.id = UCLASS_CLK,
.of_match = mt7623_pericfg_compat,
- .probe = mt7623_pericfg_probe,
+ .probe = mt7623_clk_probe,
.priv_auto = sizeof(struct mtk_clk_priv),
.ops = &mtk_clk_infrasys_ops,
.flags = DM_FLAG_PRE_RELOC,