diff options
| author | Faiz Abbas <[email protected]> | 2019-06-20 15:07:19 +0530 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2019-07-26 22:24:10 -0400 |
| commit | 461918d7df7bd356717a5f81ca58f1c8ca7ae1fb (patch) | |
| tree | 95b32f7b35940779dc322bbce3fcc7516d40a9aa | |
| parent | 697a689d76ef463623371779c78a97c13477c955 (diff) | |
ARM: dts: dra7-mmc-iodelay: Add a new pinctrl group for clk line without pullup
During a short period when the bus voltage is switched from 3.3v to 1.8v,
(to enumerate UHS mode), the mmc module is disabled and the mmc IO lines
are kept in a state according to the programmed pad mux pull type.
According to 4.2.4.2 Timing to Switch Signal Voltage in "SD Specifications
Part 1 Physical Layer Specification Version 5.00 February 22, 2016", the
host should hold CLK low for at least 5ms.
In order to keep the card line low during voltage switch, the pad mux of
mmc1_clk line should be configured to pull down.
Add a new pinctrl group for clock line without pullup to be used in boards
where mmc1_clk line is not connected to an external pullup.
Signed-off-by: Faiz Abbas <[email protected]>
| -rw-r--r-- | arch/arm/dts/am571x-idk.dts | 3 | ||||
| -rw-r--r-- | arch/arm/dts/am572x-idk.dts | 3 | ||||
| -rw-r--r-- | arch/arm/dts/dra7-mmc-iodelay.dtsi | 19 |
3 files changed, 23 insertions, 2 deletions
diff --git a/arch/arm/dts/am571x-idk.dts b/arch/arm/dts/am571x-idk.dts index debf9464403..eb5fda81f55 100644 --- a/arch/arm/dts/am571x-idk.dts +++ b/arch/arm/dts/am571x-idk.dts @@ -11,6 +11,7 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/interrupt-controller/irq.h> #include "am57xx-idk-common.dtsi" +#include "dra7-mmc-iodelay.dtsi" #include "dra72x-mmc-iodelay.dtsi" / { @@ -102,7 +103,7 @@ &mmc1 { pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; - pinctrl-0 = <&mmc1_pins_default>; + pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; pinctrl-1 = <&mmc1_pins_hs>; pinctrl-2 = <&mmc1_pins_sdr12>; pinctrl-3 = <&mmc1_pins_sdr25>; diff --git a/arch/arm/dts/am572x-idk.dts b/arch/arm/dts/am572x-idk.dts index 9212931f25d..22479485531 100644 --- a/arch/arm/dts/am572x-idk.dts +++ b/arch/arm/dts/am572x-idk.dts @@ -11,6 +11,7 @@ #include "dra74x.dtsi" #include "am572x-idk-common.dtsi" #include "am57xx-idk-common.dtsi" +#include "dra7-mmc-iodelay.dtsi" #include "dra74x-mmc-iodelay.dtsi" / { @@ -21,7 +22,7 @@ &mmc1 { pinctrl-names = "default", "hs", "sdr12", "sdr25", "sdr50", "ddr50", "sdr104"; - pinctrl-0 = <&mmc1_pins_default>; + pinctrl-0 = <&mmc1_pins_default_no_clk_pu>; pinctrl-1 = <&mmc1_pins_hs>; pinctrl-2 = <&mmc1_pins_sdr12>; pinctrl-3 = <&mmc1_pins_sdr25>; diff --git a/arch/arm/dts/dra7-mmc-iodelay.dtsi b/arch/arm/dts/dra7-mmc-iodelay.dtsi new file mode 100644 index 00000000000..4acc215ba33 --- /dev/null +++ b/arch/arm/dts/dra7-mmc-iodelay.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * MMC IOdelay values for TI's DRA7xx SoCs. + * Copyright (C) 2019 Texas Instruments + * Author: Faiz Abbas <[email protected]> + */ + +&dra7_pmx_core { + mmc1_pins_default_no_clk_pu: mmc1_pins_default_no_clk_pu { + pinctrl-single,pins = < + DRA7XX_CORE_IOPAD(0x3754, PIN_INPUT_PULLDOWN | MUX_MODE0) /* mmc1_clk.clk */ + DRA7XX_CORE_IOPAD(0x3758, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_cmd.cmd */ + DRA7XX_CORE_IOPAD(0x375c, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat0.dat0 */ + DRA7XX_CORE_IOPAD(0x3760, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat1.dat1 */ + DRA7XX_CORE_IOPAD(0x3764, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat2.dat2 */ + DRA7XX_CORE_IOPAD(0x3768, PIN_INPUT_PULLUP | MUX_MODE0) /* mmc1_dat3.dat3 */ + >; + }; +}; |