diff options
| author | Michal Simek <[email protected]> | 2026-04-30 14:03:45 +0200 |
|---|---|---|
| committer | Michal Simek <[email protected]> | 2026-06-08 08:02:39 +0200 |
| commit | 472ea8b621e18d7912db3f4141d52014628f1605 (patch) | |
| tree | 52b88f3fc12b09d1cb3745fe186b89e86043ce6d | |
| parent | 62a49635b0160c1529e7560e5f150f84a003c4d8 (diff) | |
xilinx: mbv: Allow compiler to optimize inlining in SPL
Enable CONFIG_SPL_OPTIMIZE_INLINING to let the compiler decide which
functions marked 'inline' to actually inline, rather than forcing all of
them. This reduces SPL code size by allowing the compiler to eliminate
unnecessary code duplication.
spl/u-boot-spl: all -872 text -872
Signed-off-by: Michal Simek <[email protected]>
Link: https://lore.kernel.org/r/09f2a62099abf561b91b0d3692714f0f29057d31.1777550623.git.michal.simek@amd.com
| -rw-r--r-- | configs/xilinx_mbv32_defconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/configs/xilinx_mbv32_defconfig b/configs/xilinx_mbv32_defconfig index 4a61c9eb5e3..9d0111fe8e5 100644 --- a/configs/xilinx_mbv32_defconfig +++ b/configs/xilinx_mbv32_defconfig @@ -19,6 +19,7 @@ CONFIG_TARGET_XILINX_MBV=y # CONFIG_RISCV_ISA_F is not set # CONFIG_SPL_SMP is not set # CONFIG_AVAILABLE_HARTS is not set +CONFIG_SPL_OPTIMIZE_INLINING=y CONFIG_REMAKE_ELF=y # CONFIG_EFI_LOADER is not set CONFIG_FIT=y |