diff options
| author | Steffen Kothe <[email protected]> | 2025-08-31 15:17:05 +0000 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2025-09-12 12:30:08 -0600 |
| commit | 49a3ad7a5e6aa9333c2685e98f6280ff4ae3650a (patch) | |
| tree | 96fdd719f021c38fdc626c098817a6bfc20b36f6 | |
| parent | c9ffeefeb3efedd754e3ffa3440bfeb15cea00c3 (diff) | |
arm: mach-k3: am64_hardware.h: Add CTRLMMR_MCU_RST_SRC reset cause bit mappings
AM64X SoCs use similar but not identical bit mappings like the AM62X
family.
In detail does the AM64X not support PORZ and WDT as reset caused.
Add the mapping according to the technical reference manual into the
SoC specific header.
Signed-off-by: Steffen Kothe <[email protected]>
Reviewed-by: Bryan Brattlof <[email protected]>
| -rw-r--r-- | arch/arm/mach-k3/include/mach/am64_hardware.h | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/mach-k3/include/mach/am64_hardware.h b/arch/arm/mach-k3/include/mach/am64_hardware.h index 105b42986de..95ba488ba17 100644 --- a/arch/arm/mach-k3/include/mach/am64_hardware.h +++ b/arch/arm/mach-k3/include/mach/am64_hardware.h @@ -46,6 +46,26 @@ /* Use Last 2K as Scratch pad */ #define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x7019f800 + +/* Reset Reason Detection */ +#define CTRLMMR_MCU_RST_SRC (MCU_CTRL_MMR0_BASE + 0x18178) + +/* Reset causes by bit mapping */ +#define RST_SRC_SAFETY_ERR BIT(31) +#define RST_SRC_MAIN_ESM_ERR BIT(30) +#define RST_SRC_SW_MAIN_POR_FROM_MAIN BIT(25) +#define RST_SRC_SW_MAIN_POR_FROM_MCU BIT(24) +#define RST_SRC_SW_MAIN_WARM_FROM_MAIN BIT(21) +#define RST_SRC_SW_MAIN_WARM_FROM_MCU BIT(20) +#define RST_SRC_SW_MCU_WARM_RST BIT(16) +#define RST_SRC_SMS_WARM_RST BIT(13) +#define RST_SRC_SMS_COLD_RST BIT(12) +#define RST_SRC_DEBUG_RST BIT(8) +#define RST_SRC_THERMAL_RST BIT(4) +#define RST_SRC_MAIN_RESET_PIN BIT(2) +#define RST_SRC_MCU_RESET_PIN BIT(0) + + #if defined(CONFIG_SYS_K3_SPL_ATF) && !defined(__ASSEMBLY__) #define AM64X_DEV_RTI8 127 |