diff options
| author | Marek Vasut <[email protected]> | 2021-09-14 05:25:34 +0200 |
|---|---|---|
| committer | Ramon Fried <[email protected]> | 2021-09-28 18:50:55 +0300 |
| commit | 4a60d3571be2423b68a1c34bbeece0c9d12f4bec (patch) | |
| tree | 36aa2cae5404af8b67157eb8309635dcf67b93bf | |
| parent | 4527568e3f146ac7947c8cecaa5c546e5a2d0728 (diff) | |
arm: socfpga: vining: Fix UDC controller phandle in DT
The USB peripheral controller is the DWC2 controller 1, not 0.
Update the phandle to fix UDC support on this board.
Signed-off-by: Marek Vasut <[email protected]>
Cc: Siew Chin Lim <[email protected]>
Cc: Simon Goldschmidt <[email protected]>
Cc: Tien Fong Chee <[email protected]>
| -rw-r--r-- | arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi index 9e8be282005..fb05c31d87b 100644 --- a/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi +++ b/arch/arm/dts/socfpga_cyclone5_vining_fpga-u-boot.dtsi @@ -11,7 +11,7 @@ /{ aliases { spi0 = "/soc/spi@ff705000"; - udc0 = &usb0; + udc0 = &usb1; }; }; |