riscv: create a custom CPU implementation for PolarFire SoC

PolarFire SoC needs a custom implementation of top_of_ram(), so stop
using the generic CPU & create a custom CPU instead.

Signed-off-by: Conor Dooley <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>

6 files changed, 70 insertions, 2 deletions

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 265b5320777..79867656b15 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -126,6 +126,7 @@ source "arch/riscv/cpu/cv1800b/Kconfig"
 source "arch/riscv/cpu/fu540/Kconfig"
 source "arch/riscv/cpu/fu740/Kconfig"
 source "arch/riscv/cpu/ast2700/Kconfig"
+source "arch/riscv/cpu/mpfs/Kconfig"
 source "arch/riscv/cpu/generic/Kconfig"
 source "arch/riscv/cpu/jh7110/Kconfig"
 source "arch/riscv/cpu/k1/Kconfig"
diff --git a/arch/riscv/cpu/mpfs/Kconfig b/arch/riscv/cpu/mpfs/Kconfig
new file mode 100644
index 00000000000..3e99c1aae38
--- /dev/null
+++ b/arch/riscv/cpu/mpfs/Kconfig
@@ -0,0 +1,16 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+config MICROCHIP_MPFS
+	bool
+	select ARCH_EARLY_INIT_R
+	imply CPU
+	imply CPU_RISCV
+	imply RISCV_TIMER if (RISCV_SMODE || SPL_RISCV_SMODE)
+	imply SIFIVE_CLINT if RISCV_MMODE
+	imply SPL_SIFIVE_CLINT if SPL_RISCV_MMODE
+	imply CMD_CPU
+	imply SPL_CPU
+	imply SPL_OPENSBI
+	imply SPL_LOAD_FIT
+	imply REGMAP
+	imply SYSCON
diff --git a/arch/riscv/cpu/mpfs/Makefile b/arch/riscv/cpu/mpfs/Makefile
new file mode 100644
index 00000000000..e2f62ff7711
--- /dev/null
+++ b/arch/riscv/cpu/mpfs/Makefile
@@ -0,0 +1,5 @@
+# SPDX-License-Identifier: GPL-2.0+
+
+ifneq ($(CONFIG_SPL_BUILD),y)
+obj-y += dram.o
+endif
diff --git a/arch/riscv/cpu/mpfs/dram.c b/arch/riscv/cpu/mpfs/dram.c
new file mode 100644
index 00000000000..4398d3e36c8
--- /dev/null
+++ b/arch/riscv/cpu/mpfs/dram.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Bin Meng <[email protected]>
+ */
+
+#include <asm/global_data.h>
+#include <fdtdec.h>
+#include <init.h>
+#include <linux/sizes.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define MPFS_TOP_OF_CACHED (SZ_2G + SZ_1G)
+#define MPFS_HSS_RESERVATION (SZ_4M)
+
+int dram_init(void) {
+    return fdtdec_setup_mem_size_base();
+}
+
+int dram_init_banksize(void) {
+    return fdtdec_setup_memory_banksize();
+}
+
+phys_size_t board_get_usable_ram_top(phys_size_t total_size) {
+    /*
+     * Ensure that if we run from 32-bit memory that all memory used by
+     * U-Boot is cached addresses, but also account for the reservation at
+     * the top of 32 bit cached DDR used by the HSS.
+     */
+    if (gd->ram_top >= MPFS_TOP_OF_CACHED - MPFS_HSS_RESERVATION)
+        return MPFS_TOP_OF_CACHED - MPFS_HSS_RESERVATION - 1;
+    /*
+     * If we don't find a 32 bit region just return the top of memory.
+     * If the address is a 32-bit region, but fits beneath the HSS'
+     * reservation, ram_top is adequate also.
+     */
+    return gd->ram_top;
+}
\ No newline at end of file
diff --git a/arch/riscv/include/asm/arch-mpfs/clk.h b/arch/riscv/include/asm/arch-mpfs/clk.h
new file mode 100644
index 00000000000..fbb1399f3c8
--- /dev/null
+++ b/arch/riscv/include/asm/arch-mpfs/clk.h
@@ -0,0 +1,8 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+
+#ifndef __ASM_RISCV_ARCH_MPFS_CLK_H
+#define __ASM_RISCV_ARCH_MPFS_CLK_H
+
+/* Note: This is a placeholder header for driver compilation. */
+
+#endif
diff --git a/board/microchip/mpfs_generic/Kconfig b/board/microchip/mpfs_generic/Kconfig
index 8dcf55a0311..49663a4c562 100644
--- a/board/microchip/mpfs_generic/Kconfig
+++ b/board/microchip/mpfs_generic/Kconfig
@@ -7,7 +7,7 @@ config SYS_VENDOR
 	default "microchip"
 
 config SYS_CPU
-	default "generic"
+	default "mpfs"
 
 config SYS_CONFIG_NAME
 	default "microchip_mpfs_generic"
@@ -18,7 +18,7 @@ config TEXT_BASE
 
 config BOARD_SPECIFIC_OPTIONS # dummy
 	def_bool y
-	select GENERIC_RISCV
+	select MICROCHIP_MPFS
 	select BOARD_EARLY_INIT_F
 	select BOARD_LATE_INIT
 	imply SMP