diff options
| author | Adam Ford <[email protected]> | 2025-03-18 18:38:29 -0500 |
|---|---|---|
| committer | Fabio Estevam <[email protected]> | 2025-03-19 13:17:21 -0300 |
| commit | 4e73c627cb5e53a058b8dbc2ede32f8a473acdd1 (patch) | |
| tree | 5f95de669150a7c09cafb1fa5d143aacaab28ec3 | |
| parent | 8bc3542384e3a1219e5ffb62b79d16dddc1b1fb9 (diff) | |
clk: imx6q: Properly handle imx6qp ECSPI clk_sels
The ECSPI clock has the ability to select between pll3_60m and
osc on the imx6qp, where it's fixed on other variants. Fix this
by adding using a helper function to determine SoC variant and
register the clock accordingly.
Signed-off-by: Adam Ford <[email protected]>
Reviewed-by: Michael Trimarchi <[email protected]>
Reviewed-by: Peng Fan <[email protected]>
| -rw-r--r-- | drivers/clk/imx/clk-imx6q.c | 14 |
1 files changed, 12 insertions, 2 deletions
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index df9f0285e1e..ba75fd1aad6 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -35,6 +35,7 @@ static const char *const usdhc_sels[] = { "pll2_pfd2_396m", "pll2_pfd0_352m", }; static const char *const periph_sels[] = { "periph_pre", "periph_clk2", }; static const char *const periph_pre_sels[] = { "pll2_bus", "pll2_pfd2_396m", "pll2_pfd0_352m", "pll2_198m", }; +static const char *const ecspi_sels[] = { "pll3_60m", "osc", }; static int imx6q_clk_probe(struct udevice *dev) { @@ -78,6 +79,11 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_mux("usdhc4_sel", base + 0x1c, 19, 1, usdhc_sels, ARRAY_SIZE(usdhc_sels))); + if (of_machine_is_compatible("fsl,imx6qp")) + clk_dm(IMX6QDL_CLK_ECSPI_SEL, + imx_clk_mux("ecspi_sel", base + 0x38, 18, 1, ecspi_sels, + ARRAY_SIZE(ecspi_sels))); + clk_dm(IMX6QDL_CLK_USDHC1_PODF, imx_clk_divider("usdhc1_podf", "usdhc1_sel", base + 0x24, 11, 3)); @@ -91,8 +97,12 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_divider("usdhc4_podf", "usdhc4_sel", base + 0x24, 22, 3)); - clk_dm(IMX6QDL_CLK_ECSPI_ROOT, - imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6)); + if (of_machine_is_compatible("fsl,imx6qp")) + clk_dm(IMX6QDL_CLK_ECSPI_ROOT, + imx_clk_divider("ecspi_root", "ecspi_sel", base + 0x38, 19, 6)); + else + clk_dm(IMX6QDL_CLK_ECSPI_ROOT, + imx_clk_divider("ecspi_root", "pll3_60m", base + 0x38, 19, 6)); clk_dm(IMX6QDL_CLK_ECSPI1, imx_clk_gate2("ecspi1", "ecspi_root", base + 0x6c, 0)); |