diff options
| author | Tingting Meng <[email protected]> | 2025-04-15 09:55:35 +0800 |
|---|---|---|
| committer | Tien Fong Chee <[email protected]> | 2025-04-22 11:47:40 +0800 |
| commit | 52891fda68977e321043c2c4e04f6f3d55352726 (patch) | |
| tree | 73659470422d8b508afa6d5db4fe3f24b9d06aad | |
| parent | d0bf7bebfd5c045b96686e314177b2e01d0695e3 (diff) | |
arm: dts: agilex5: Update CCU configuration
Cache allocation for dirty writes in the CCU system cache was disabled
for performance optimization.
Signed-off-by: Tingting Meng <[email protected]>
| -rw-r--r-- | arch/arm/dts/socfpga_agilex5-u-boot.dtsi | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi index b34af85c58d..874e71b5ca4 100644 --- a/arch/arm/dts/socfpga_agilex5-u-boot.dtsi +++ b/arch/arm/dts/socfpga_agilex5-u-boot.dtsi @@ -208,7 +208,8 @@ intel,offset-settings = /* DMIUSMCTCR */ <0x00000300 0x00000001 0x00000003>, - <0x00000300 0x00000003 0x00000003>; + <0x00000300 0x00000003 0x00000003>, + <0x00000308 0x00000004 0x0000001F>; bootph-all; }; @@ -218,7 +219,8 @@ intel,offset-settings = /* DMIUSMCTCR */ <0x00000300 0x00000001 0x00000003>, - <0x00000300 0x00000003 0x00000003>; + <0x00000300 0x00000003 0x00000003>, + <0x00000308 0x00000004 0x0000001F>; bootph-all; }; }; |