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authorAbhash Kumar Jha <[email protected]>2026-05-15 13:47:45 +0530
committerTom Rini <[email protected]>2026-05-29 14:17:14 -0600
commit59d52a9975777b959e3bbb0b5e08b64dd67a705f (patch)
tree14608e31c52c1881506fe31ade455732cea5366e
parentddd1f2192de473a05ff79b8e52a5b72cffd5ea79 (diff)
board: ti: j722s: add processor ACL entry for wkup_r5
On the j722s platform, the DM firmware resets the wkup_r5 core at boot to enable both of its TCM memories. This reset sequence involves three steps: - Acquiring processor ownership of wkup_r5 - Configuring the core and requesting a reset via TIFS - Releasing ownership. When the Linux remoteproc driver comes up, it acquires ownership of wkup_r5 to query its state, making A53_2 the new owner. During system suspend, TIFS saves the processor ACL[1] table to DDR as part of its context. On resume, TIFS restores the ACL table, leaving A53_2 as the owner of wkup_r5. At this point, DM (WKUP_0_R5_0 host[2]) no longer has ownership and is therefore unable to perform the reset sequence it needs, causing it to crash. To fix this, configure the wkup_r5[3] processor with dual ownership: - WKUP_0_R5_0 (Secure) as primary owner. - A53_2 (Non-Secure) as secondary owner. [1] https://software-dl.ti.com/tisci/esd/latest/3_boardcfg/BOARDCFG_SEC.html#pub-boardcfg-proc-acl [2] https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j722s/hosts.html [3] https://software-dl.ti.com/tisci/esd/latest/5_soc_doc/j722s/processors.html Signed-off-by: Abhash Kumar Jha <[email protected]> Reviewed-by: Neha Malcom Francis <[email protected]>
-rw-r--r--board/ti/j722s/sec-cfg.yaml6
1 files changed, 3 insertions, 3 deletions
diff --git a/board/ti/j722s/sec-cfg.yaml b/board/ti/j722s/sec-cfg.yaml
index e9a9d526cfb..b68b305b6bb 100644
--- a/board/ti/j722s/sec-cfg.yaml
+++ b/board/ti/j722s/sec-cfg.yaml
@@ -16,9 +16,9 @@ sec-cfg:
size: 164
proc_acl_entries:
-
- processor_id: 0
- proc_access_master: 0
- proc_access_secondary: [0, 0, 0]
+ processor_id: 0x1
+ proc_access_master: 0x23
+ proc_access_secondary: [0xC, 0, 0]
-
processor_id: 0
proc_access_master: 0