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authorChristian Marangi <[email protected]>2024-08-03 10:40:34 +0200
committerTom Rini <[email protected]>2024-08-19 16:14:43 -0600
commit5dd509788dd1cd73cd8ac3881d026c5b33a725a5 (patch)
treec14166a6596ace5c8292d6ad4b38d5dcc3313222
parent6becf9ba1ab82af6f4fcf9f4d0da38f9c75212d2 (diff)
clk: mediatek: mt7986: fix wrong shift for PCIe clocks
Fix wrong shift for PCIe clocks. This cause the PCIe port to malfunction as the gate clocks weren't correctly enabled. Signed-off-by: Christian Marangi <[email protected]>
-rw-r--r--drivers/clk/mediatek/clk-mt7986.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index efc3d4120b7..1e8c3278346 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -504,8 +504,8 @@ static const struct mtk_gate infracfg_ao_gates[] = {
GATE_INFRA2(CK_INFRA_IUSB_SYS_CK, "infra_iusb_sys", CK_INFRA_USB_SYS_CK,
2),
GATE_INFRA2(CK_INFRA_IUSB_CK, "infra_iusb", CK_INFRA_USB_CK, 3),
- GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie", CK_INFRA_PCIE_CK, 13),
- GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 15),
+ GATE_INFRA2(CK_INFRA_IPCIE_CK, "infra_ipcie", CK_INFRA_PCIE_CK, 12),
+ GATE_INFRA2(CK_INFRA_IPCIER_CK, "infra_ipcier", CK_INFRA_F26M_CK0, 14),
GATE_INFRA2(CK_INFRA_IPCIEB_CK, "infra_ipcieb", CK_INFRA_133M_PHCK, 15),
};