board: nxp: common: fix PFUZE100 DM build and unify DM/non-DM handling

Switch PFUZE100 object linkage to be phase-aware and fix build issues
when using driver model PMIC support.

The PFUZE100 helper code is reworked to:
- Build pfuze.o only when CONFIG_(SPL_)DM_PMIC_PFUZE100 is enabled
- Use CONFIG_IS_ENABLED(DM_PMIC_PFUZE100) for proper DM/non-DM selection
- Align function signatures and implementations with DM PMIC APIs
- Use udevice-based pmic access for DM and legacy pmic for non-DM
- Avoid mixing struct pmic and struct udevice in the same build
  configuration

No functional change intended beyond fixing DM support and build
consistency.

Signed-off-by: Peng Fan <[email protected]>

3 files changed, 50 insertions, 50 deletions

diff --git a/board/nxp/common/Makefile b/board/nxp/common/Makefile
index ed102ae7bf7..dafd3717948 100644
--- a/board/nxp/common/Makefile
+++ b/board/nxp/common/Makefile
@@ -57,7 +57,7 @@ obj-$(CONFIG_TARGET_P5040DS)		+= ics307_clk.o
 ifeq ($(CONFIG_$(PHASE_)POWER_LEGACY),y)
 obj-$(CONFIG_POWER_PFUZE100)	+= pfuze.o
 endif
-obj-$(CONFIG_DM_PMIC_PFUZE100)	+= pfuze.o
+obj-$(CONFIG_$(PHASE_)DM_PMIC_PFUZE100)	+= pfuze.o
 obj-$(CONFIG_POWER_MC34VR500)	+= mc34vr500.o
 ifneq (,$(filter $(SOC), imx8m imx8ulp imx9))
 obj-y				+= mmc.o
diff --git a/board/nxp/common/pfuze.c b/board/nxp/common/pfuze.c
index 0d7a94fd232..179cc605da0 100644
--- a/board/nxp/common/pfuze.c
+++ b/board/nxp/common/pfuze.c
@@ -7,14 +7,14 @@
 #include <power/pmic.h>
 #include <power/pfuze100_pmic.h>
 
-#ifndef CONFIG_DM_PMIC_PFUZE100
-int pfuze_mode_init(struct pmic *p, u32 mode)
+#if CONFIG_IS_ENABLED(DM_PMIC_PFUZE100)
+int pfuze_mode_init(struct udevice *dev, u32 mode)
 {
 	unsigned char offset, i, switch_num;
 	u32 id;
 	int ret;
 
-	pmic_reg_read(p, PFUZE100_DEVICEID, &id);
+	id = pmic_reg_read(dev, PFUZE100_DEVICEID);
 	id = id & 0xf;
 
 	if (id == 0) {
@@ -28,14 +28,14 @@ int pfuze_mode_init(struct pmic *p, u32 mode)
 		return -EINVAL;
 	}
 
-	ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
+	ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode);
 	if (ret < 0) {
 		printf("Set SW1AB mode error!\n");
 		return ret;
 	}
 
 	for (i = 0; i < switch_num - 1; i++) {
-		ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
+		ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode);
 		if (ret < 0) {
 			printf("Set switch 0x%x mode error!\n",
 			       offset + i * SWITCH_SIZE);
@@ -46,58 +46,54 @@ int pfuze_mode_init(struct pmic *p, u32 mode)
 	return ret;
 }
 
-struct pmic *pfuze_common_init(unsigned char i2cbus)
+struct udevice *pfuze_common_init(void)
 {
-	struct pmic *p;
+	struct udevice *dev;
 	int ret;
-	unsigned int reg;
-
-	ret = power_pfuze100_init(i2cbus);
-	if (ret)
-		return NULL;
+	unsigned int reg, dev_id, rev_id;
 
-	p = pmic_get("PFUZE100");
-	ret = pmic_probe(p);
-	if (ret)
+	ret = pmic_get("pfuze100@8", &dev);
+	if (ret == -ENODEV)
 		return NULL;
 
-	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
-	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
+	dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+	rev_id = pmic_reg_read(dev, PFUZE100_REVID);
+	printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
 
 	/* Set SW1AB stanby volage to 0.975V */
-	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
+	reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
 	reg &= ~SW1x_STBY_MASK;
 	reg |= SW1x_0_975V;
-	pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
+	pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
 
 	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
-	pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
+	reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
 	reg &= ~SW1xCONF_DVSSPEED_MASK;
 	reg |= SW1xCONF_DVSSPEED_4US;
-	pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
+	pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
 
 	/* Set SW1C standby voltage to 0.975V */
-	pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
+	reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
 	reg &= ~SW1x_STBY_MASK;
 	reg |= SW1x_0_975V;
-	pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
+	pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
 
 	/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
-	pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
+	reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
 	reg &= ~SW1xCONF_DVSSPEED_MASK;
 	reg |= SW1xCONF_DVSSPEED_4US;
-	pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
+	pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
 
-	return p;
+	return dev;
 }
-#elif defined(CONFIG_DM_PMIC)
-int pfuze_mode_init(struct udevice *dev, u32 mode)
+#else
+int pfuze_mode_init(struct pmic *p, u32 mode)
 {
 	unsigned char offset, i, switch_num;
 	u32 id;
 	int ret;
 
-	id = pmic_reg_read(dev, PFUZE100_DEVICEID);
+	pmic_reg_read(p, PFUZE100_DEVICEID, &id);
 	id = id & 0xf;
 
 	if (id == 0) {
@@ -111,14 +107,14 @@ int pfuze_mode_init(struct udevice *dev, u32 mode)
 		return -EINVAL;
 	}
 
-	ret = pmic_reg_write(dev, PFUZE100_SW1ABMODE, mode);
+	ret = pmic_reg_write(p, PFUZE100_SW1ABMODE, mode);
 	if (ret < 0) {
 		printf("Set SW1AB mode error!\n");
 		return ret;
 	}
 
 	for (i = 0; i < switch_num - 1; i++) {
-		ret = pmic_reg_write(dev, offset + i * SWITCH_SIZE, mode);
+		ret = pmic_reg_write(p, offset + i * SWITCH_SIZE, mode);
 		if (ret < 0) {
 			printf("Set switch 0x%x mode error!\n",
 			       offset + i * SWITCH_SIZE);
@@ -129,44 +125,48 @@ int pfuze_mode_init(struct udevice *dev, u32 mode)
 	return ret;
 }
 
-struct udevice *pfuze_common_init(void)
+struct pmic *pfuze_common_init(unsigned char i2cbus)
 {
-	struct udevice *dev;
+	struct pmic *p;
 	int ret;
-	unsigned int reg, dev_id, rev_id;
+	unsigned int reg;
 
-	ret = pmic_get("pfuze100@8", &dev);
-	if (ret == -ENODEV)
+	ret = power_pfuze100_init(i2cbus);
+	if (ret)
 		return NULL;
 
-	dev_id = pmic_reg_read(dev, PFUZE100_DEVICEID);
-	rev_id = pmic_reg_read(dev, PFUZE100_REVID);
-	printf("PMIC: PFUZE100! DEV_ID=0x%x REV_ID=0x%x\n", dev_id, rev_id);
+	p = pmic_get("PFUZE100");
+	ret = pmic_probe(p);
+	if (ret)
+		return NULL;
+
+	pmic_reg_read(p, PFUZE100_DEVICEID, &reg);
+	printf("PMIC:  PFUZE100 ID=0x%02x\n", reg);
 
 	/* Set SW1AB stanby volage to 0.975V */
-	reg = pmic_reg_read(dev, PFUZE100_SW1ABSTBY);
+	pmic_reg_read(p, PFUZE100_SW1ABSTBY, &reg);
 	reg &= ~SW1x_STBY_MASK;
 	reg |= SW1x_0_975V;
-	pmic_reg_write(dev, PFUZE100_SW1ABSTBY, reg);
+	pmic_reg_write(p, PFUZE100_SW1ABSTBY, reg);
 
 	/* Set SW1AB/VDDARM step ramp up time from 16us to 4us/25mV */
-	reg = pmic_reg_read(dev, PFUZE100_SW1ABCONF);
+	pmic_reg_read(p, PFUZE100_SW1ABCONF, &reg);
 	reg &= ~SW1xCONF_DVSSPEED_MASK;
 	reg |= SW1xCONF_DVSSPEED_4US;
-	pmic_reg_write(dev, PFUZE100_SW1ABCONF, reg);
+	pmic_reg_write(p, PFUZE100_SW1ABCONF, reg);
 
 	/* Set SW1C standby voltage to 0.975V */
-	reg = pmic_reg_read(dev, PFUZE100_SW1CSTBY);
+	pmic_reg_read(p, PFUZE100_SW1CSTBY, &reg);
 	reg &= ~SW1x_STBY_MASK;
 	reg |= SW1x_0_975V;
-	pmic_reg_write(dev, PFUZE100_SW1CSTBY, reg);
+	pmic_reg_write(p, PFUZE100_SW1CSTBY, reg);
 
 	/* Set SW1C/VDDSOC step ramp up time from 16us to 4us/25mV */
-	reg = pmic_reg_read(dev, PFUZE100_SW1CCONF);
+	pmic_reg_read(p, PFUZE100_SW1CCONF, &reg);
 	reg &= ~SW1xCONF_DVSSPEED_MASK;
 	reg |= SW1xCONF_DVSSPEED_4US;
-	pmic_reg_write(dev, PFUZE100_SW1CCONF, reg);
+	pmic_reg_write(p, PFUZE100_SW1CCONF, reg);
 
-	return dev;
+	return p;
 }
 #endif
diff --git a/board/nxp/common/pfuze.h b/board/nxp/common/pfuze.h
index 45b49afaeb7..da89853bd20 100644
--- a/board/nxp/common/pfuze.h
+++ b/board/nxp/common/pfuze.h
@@ -6,7 +6,7 @@
 #ifndef __PFUZE_BOARD_HELPER__
 #define __PFUZE_BOARD_HELPER__
 
-#ifdef CONFIG_DM_PMIC_PFUZE100
+#if CONFIG_IS_ENABLED(DM_PMIC_PFUZE100)
 struct udevice *pfuze_common_init(void);
 int pfuze_mode_init(struct udevice *dev, u32 mode);
 #else