diff options
| author | Naresh Kumar Ravulapalli <[email protected]> | 2025-08-18 21:24:04 -0700 |
|---|---|---|
| committer | Tien Fong Chee <[email protected]> | 2025-09-30 14:29:52 +0800 |
| commit | 65261e83f3b1fd5e17ff361d167ae035e2954502 (patch) | |
| tree | 60e6042e7001cadcb19acb9a1a2f20bbd9df4cb5 | |
| parent | 2a7771166ea903726c8d9d919ddcd5526c882459 (diff) | |
configs: socfpga: Add CRC32 support
CRC32 support for SoC64 devices is added.
Signed-off-by: Naresh Kumar Ravulapalli <[email protected]>
Reviewed-by: Tien Fong Chee <[email protected]>
| -rw-r--r-- | configs/socfpga_agilex_defconfig | 1 | ||||
| -rw-r--r-- | configs/socfpga_n5x_defconfig | 1 | ||||
| -rw-r--r-- | configs/socfpga_stratix10_defconfig | 1 |
3 files changed, 3 insertions, 0 deletions
diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 1c3664bc0d7..44c12db08b5 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -38,6 +38,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 +CONFIG_SPL_CRC32=y CONFIG_SPL_CACHE=y CONFIG_SPL_MTD=y CONFIG_SPL_SPI_FLASH_MTD=y diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig index 879556614f6..d501fcddf3d 100644 --- a/configs/socfpga_n5x_defconfig +++ b/configs/socfpga_n5x_defconfig @@ -37,6 +37,7 @@ CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 CONFIG_SPL_CACHE=y +CONFIG_SPL_CRC32=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x3c00000 CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex" diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 90134d8f3f3..fe191d09714 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -41,6 +41,7 @@ CONFIG_SPL_SYS_MALLOC=y CONFIG_SPL_HAS_CUSTOM_MALLOC_START=y CONFIG_SPL_CUSTOM_SYS_MALLOC_ADDR=0x3fa00000 CONFIG_SPL_SYS_MALLOC_SIZE=0x500000 +CONFIG_SPL_CRC32=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x3C00000 CONFIG_SPL_TARGET="spl/u-boot-spl-dtb.hex" |