diff options
| author | Pali Rohár <[email protected]> | 2022-04-29 20:27:34 +0200 |
|---|---|---|
| committer | Jaehoon Chung <[email protected]> | 2022-07-27 15:19:08 +0900 |
| commit | 6dcf1c28dd4344e73fb3108c037b5b9093852328 (patch) | |
| tree | a03dd1926c21b65d0818e4e491f24325a48afcef | |
| parent | 86feeab3dc71977afb70f595e42060ce324086d0 (diff) | |
mmc: fsl_esdhc: Fix 'Internal clock never stabilised.' error
Only newer eSDHC controllers set PRSSTAT_SDSTB flag. So do not wait until
flag PRSSTAT_SDSTB is set on old pre-2.2 controllers. Instead sleep for
fixed amount of time like it was before commit 6f883e501b65 ("mmc:
fsl_esdhc: Add emmc hs200 support").
This change fixes error 'Internal clock never stabilised.' which is printed
on P2020 board at every access to SD card.
Fixes: 6f883e501b65 ("mmc: fsl_esdhc: Add emmc hs200 support")
Signed-off-by: Pali Rohár <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
Reviewed-by: Jaehoon Chung <[email protected]>
| -rw-r--r-- | drivers/mmc/fsl_esdhc.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index b49a7b425b9..ca5a87969f8 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -504,6 +504,7 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) u32 time_out; u32 value; uint clk; + u32 hostver; if (clock < mmc->cfg->f_min) clock = mmc->cfg->f_min; @@ -544,6 +545,14 @@ static void set_sysctl(struct fsl_esdhc_priv *priv, struct mmc *mmc, uint clock) esdhc_clrsetbits32(®s->sysctl, SYSCTL_CLOCK_MASK, clk); + /* Only newer eSDHC controllers set PRSSTAT_SDSTB flag */ + hostver = esdhc_read32(&priv->esdhc_regs->hostver); + if (HOSTVER_VENDOR(hostver) <= VENDOR_V_22) { + udelay(10000); + esdhc_setbits32(®s->sysctl, SYSCTL_PEREN | SYSCTL_CKEN); + return; + } + time_out = 20; value = PRSSTAT_SDSTB; while (!(esdhc_read32(®s->prsstat) & value)) { @@ -563,6 +572,7 @@ static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable) struct fsl_esdhc *regs = priv->esdhc_regs; u32 value; u32 time_out; + u32 hostver; value = esdhc_read32(®s->sysctl); @@ -573,6 +583,13 @@ static void esdhc_clock_control(struct fsl_esdhc_priv *priv, bool enable) esdhc_write32(®s->sysctl, value); + /* Only newer eSDHC controllers set PRSSTAT_SDSTB flag */ + hostver = esdhc_read32(&priv->esdhc_regs->hostver); + if (HOSTVER_VENDOR(hostver) <= VENDOR_V_22) { + udelay(10000); + return; + } + time_out = 20; value = PRSSTAT_SDSTB; while (!(esdhc_read32(®s->prsstat) & value)) { |