diff options
| author | Weijie Gao <[email protected]> | 2024-12-17 16:39:16 +0800 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2024-12-31 10:58:52 -0600 |
| commit | 6e45549f4dac42748d66462e04f940ef6737289d (patch) | |
| tree | b26eba1216b3f46c633331048d27588a1739053c | |
| parent | 25fb58e88aba0c4af0af554d7b141be3f2e5e0b5 (diff) | |
clk: mediatek: mt7629: fix parent clock of some top clock muxes
According to the mt7629 programming guide, the CLK_TOP_F10M_REF_SEL
shares the same parent selection with CLK_TOP_IRRX_SEL, while the
present parent selection for CLK_TOP_F10M_REF_SEL is actually used
for CLK_TOP_SGMII_REF_1_SEL.
Signed-off-by: Weijie Gao <[email protected]>
| -rw-r--r-- | drivers/clk/mediatek/clk-mt7629.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c index 0c796a1788a..380ab9b9b0b 100644 --- a/drivers/clk/mediatek/clk-mt7629.c +++ b/drivers/clk/mediatek/clk-mt7629.c @@ -186,7 +186,7 @@ static const int pwm_parents[] = { CLK_TOP_UNIVPLL2_D4 }; -static const int f10m_ref_parents[] = { +static const int sgmii_ref_1_parents[] = { CLK_XTAL, CLK_TOP_SGMIIPLL_D2 }; @@ -369,7 +369,7 @@ static const struct mtk_composite top_muxes[] = { /* CLK_CFG_1 */ MUX_GATE(CLK_TOP_PWM_SEL, pwm_parents, 0x50, 0, 2, 7), - MUX_GATE(CLK_TOP_F10M_REF_SEL, f10m_ref_parents, 0x50, 8, 1, 15), + MUX_GATE(CLK_TOP_F10M_REF_SEL, irrx_parents, 0x50, 8, 1, 15), MUX_GATE(CLK_TOP_NFI_INFRA_SEL, nfi_infra_parents, 0x50, 16, 4, 23), MUX_GATE(CLK_TOP_FLASH_SEL, flash_parents, 0x50, 24, 3, 31), @@ -412,7 +412,7 @@ static const struct mtk_composite top_muxes[] = { /* CLK_CFG_8 */ MUX_GATE(CLK_TOP_CRYPTO_SEL, crypto_parents, 0xC0, 0, 3, 7), - MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, f10m_ref_parents, 0xC0, 8, 1, 15), + MUX_GATE(CLK_TOP_SGMII_REF_1_SEL, sgmii_ref_1_parents, 0xC0, 8, 1, 15), MUX_GATE(CLK_TOP_10M_SEL, gpt10m_parents, 0xC0, 16, 1, 23), }; |