diff options
| author | Ye Li <[email protected]> | 2020-05-03 22:19:52 +0800 |
|---|---|---|
| committer | Stefano Babic <[email protected]> | 2020-05-10 20:55:20 +0200 |
| commit | 70487ff386c0b7ee40b83aff219f8b36829e8b13 (patch) | |
| tree | a9221d36c5f3d7ada07085856207a074961e91d6 | |
| parent | 634fe73eedb9551a13296f356afae67539583f17 (diff) | |
imx8mm: Load fuse for TMU TCALIV and TASR
On iMX8MM, the default value of TMU registers TCALIV and TASR need
be loaded from fuse. HW won't do this, it expect SW loads them before
using TMU.
Reviewed-by: Bai Ping <[email protected]>
Signed-off-by: Ye Li <[email protected]>
Signed-off-by: Peng Fan <[email protected]>
| -rw-r--r-- | arch/arm/mach-imx/imx8m/soc.c | 28 |
1 files changed, 27 insertions, 1 deletions
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c index 89229da3b62..dcec83e6248 100644 --- a/arch/arm/mach-imx/imx8m/soc.c +++ b/arch/arm/mach-imx/imx8m/soc.c @@ -1,6 +1,6 @@ // SPDX-License-Identifier: GPL-2.0+ /* - * Copyright 2017 NXP + * Copyright 2017-2019 NXP * * Peng Fan <[email protected]> */ @@ -448,3 +448,29 @@ int arch_misc_init(void) return 0; } #endif + +void imx_tmu_arch_init(void *reg_base) +{ + if (is_imx8mm()) { + /* Load TCALIV and TASR from fuses */ + struct ocotp_regs *ocotp = + (struct ocotp_regs *)OCOTP_BASE_ADDR; + struct fuse_bank *bank = &ocotp->bank[3]; + struct fuse_bank3_regs *fuse = + (struct fuse_bank3_regs *)bank->fuse_regs; + + u32 tca_rt, tca_hr, tca_en; + u32 buf_vref, buf_slope; + + tca_rt = fuse->ana0 & 0xFF; + tca_hr = (fuse->ana0 & 0xFF00) >> 8; + tca_en = (fuse->ana0 & 0x2000000) >> 25; + + buf_vref = (fuse->ana0 & 0x1F00000) >> 20; + buf_slope = (fuse->ana0 & 0xF0000) >> 16; + + writel(buf_vref | (buf_slope << 16), (ulong)reg_base + 0x28); + writel((tca_en << 31) | (tca_hr << 16) | tca_rt, + (ulong)reg_base + 0x30); + } +} |