Merge tag 'u-boot-imx-master-20260206' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx

CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/29216

- Convert imx8mn_var_som to OF_UPSTREAM and several cleanups.
- Fix ele_ahab buid error on imx93_qsb.
- Add i.MX95 EVK remoteproc support.
- Several i.MX8/9 EVK cleanups.

37 files changed, 308 insertions, 1009 deletions

diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 3cd762977cb..82ad3035308 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -888,7 +888,6 @@ dtb-$(CONFIG_ARCH_IMX8M) += \
 	imx8mm-mx8menlo.dtb \
 	imx8mm-phg.dtb \
 	imx8mq-cm.dtb \
-	imx8mn-var-som-symphony.dtb \
 	imx8mq-mnt-reform2.dtb \
 	imx8mq-phanbell.dtb \
 	imx8mp-data-modul-edm-sbc.dtb \
diff --git a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
index 2bbc4a49418..a94a571df5e 100644
--- a/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
+++ b/arch/arm/dts/imx8mn-var-som-symphony-u-boot.dtsi
@@ -3,52 +3,7 @@
  * Copyright 2021 Collabora Ltd.
  */
 
-#include "imx8mn-u-boot.dtsi"
-
-&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
-	bootph-pre-ram;
-};
-
-&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
-	bootph-pre-ram;
-};
-
-&eeprom_som {
-	#address-cells = <1>;
-	#size-cells = <1>;
-	eth_mac_address: eth-mac-address@19 {
-		reg = <0x19 0x06>;
-	};
-};
-
-&fec1 {
-	nvmem-cells = <&eth_mac_address>;
-	nvmem-cell-names = "mac-address";
-};
-
-&gpio1 {
-	bootph-pre-ram;
-};
-
-&gpio2 {
-	bootph-pre-ram;
-};
-
-&gpio4 {
-	bootph-pre-ram;
-};
-
-&i2c1 {
-	bootph-all;
-};
-
-&pinctrl_i2c1 {
-	bootph-all;
-};
-
-&pinctrl_pmic {
-	bootph-pre-ram;
-};
+#include "imx8mn-var-som-u-boot.dtsi"
 
 &pinctrl_reg_usdhc2_vmmc {
 	bootph-pre-ram;
@@ -62,14 +17,6 @@
 	bootph-pre-ram;
 };
 
-&pinctrl_usdhc3 {
-	bootph-pre-ram;
-};
-
-&pinctrl_wdog {
-	bootph-pre-ram;
-};
-
 &uart4 {
 	bootph-pre-ram;
 };
@@ -77,11 +24,3 @@
 &usdhc2 {
 	bootph-pre-ram;
 };
-
-&usdhc3 {
-	bootph-pre-ram;
-};
-
-&eeprom_som {
-	bootph-all;
-};
diff --git a/arch/arm/dts/imx8mn-var-som-symphony.dts b/arch/arm/dts/imx8mn-var-som-symphony.dts
deleted file mode 100644
index 5c8e4e81752..00000000000
--- a/arch/arm/dts/imx8mn-var-som-symphony.dts
+++ /dev/null
@@ -1,236 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2019-2020 Variscite Ltd.
- * Copyright (C) 2020 Krzysztof Kozlowski <[email protected]>
- */
-
-/dts-v1/;
-
-#include "imx8mn-var-som.dtsi"
-
-/ {
-	model = "Variscite VAR-SOM-MX8MN Symphony evaluation board";
-	compatible = "variscite,var-som-mx8mn-symphony", "variscite,var-som-mx8mn", "fsl,imx8mn";
-
-	reg_usdhc2_vmmc: regulator-usdhc2-vmmc {
-		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>;
-		regulator-name = "VSD_3V3";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&gpio4 22 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-
-	gpio-keys {
-		compatible = "gpio-keys";
-
-		key-back {
-			label = "Back";
-			gpios = <&pca9534 1 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_BACK>;
-		};
-
-		key-home {
-			label = "Home";
-			gpios = <&pca9534 2 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_HOME>;
-		};
-
-		key-menu {
-			label = "Menu";
-			gpios = <&pca9534 3 GPIO_ACTIVE_LOW>;
-			linux,code = <KEY_MENU>;
-		};
-	};
-
-	leds {
-		compatible = "gpio-leds";
-
-		led {
-			label = "Heartbeat";
-			gpios = <&pca9534 0 GPIO_ACTIVE_LOW>;
-			linux,default-trigger = "heartbeat";
-		};
-	};
-};
-
-&i2c2 {
-	clock-frequency = <400000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c2>;
-	status = "okay";
-
-	pca9534: gpio@20 {
-		compatible = "nxp,pca9534";
-		reg = <0x20>;
-		gpio-controller;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_pca9534>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <7 IRQ_TYPE_EDGE_FALLING>;
-		#gpio-cells = <2>;
-		wakeup-source;
-
-		/* USB 3.0 OTG (usbotg1) / SATA port switch, set to USB 3.0 */
-		usb3-sata-sel-hog {
-			gpio-hog;
-			gpios = <4 GPIO_ACTIVE_HIGH>;
-			output-low;
-			line-name = "usb3_sata_sel";
-		};
-
-		som-vselect-hog {
-			gpio-hog;
-			gpios = <6 GPIO_ACTIVE_HIGH>;
-			output-low;
-			line-name = "som_vselect";
-		};
-
-		enet-sel-hog {
-			gpio-hog;
-			gpios = <7 GPIO_ACTIVE_HIGH>;
-			output-low;
-			line-name = "enet_sel";
-		};
-	};
-
-	extcon_usbotg1: typec@3d {
-		compatible = "nxp,ptn5150";
-		reg = <0x3d>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <11 IRQ_TYPE_LEVEL_LOW>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_ptn5150>;
-		status = "okay";
-	};
-};
-
-&i2c3 {
-	/* Capacitive touch controller */
-	ft5x06_ts: touchscreen@38 {
-		compatible = "edt,edt-ft5406";
-		reg = <0x38>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_captouch>;
-		interrupt-parent = <&gpio5>;
-		interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
-
-		touchscreen-size-x = <800>;
-		touchscreen-size-y = <480>;
-		touchscreen-inverted-x;
-		touchscreen-inverted-y;
-	};
-
-	rtc@68 {
-		compatible = "dallas,ds1337";
-		reg = <0x68>;
-	};
-};
-
-/* Header */
-&uart1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart1>;
-	status = "okay";
-};
-
-/* Header */
-&uart3 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart3>;
-	status = "okay";
-};
-
-&usbotg1 {
-	disable-over-current;
-	extcon = <&extcon_usbotg1>, <&extcon_usbotg1>;
-};
-
-&pinctrl_fec1 {
-	fsl,pins = <
-		MX8MN_IOMUXC_ENET_MDC_ENET1_MDC			0x3
-		MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
-		MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
-		MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
-		MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
-		MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
-		MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
-		MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
-		MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
-		MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
-		MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
-		MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
-		MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
-		MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
-		/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
-	>;
-};
-
-&pinctrl_fec1_sleep {
-	fsl,pins = <
-		MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16		0x120
-		MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17		0x120
-		MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18		0x120
-		MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19		0x120
-		MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20		0x120
-		MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21		0x120
-		MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29		0x120
-		MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28		0x120
-		MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27		0x120
-		MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26		0x120
-		MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23		0x120
-		MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25		0x120
-		MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24		0x120
-		MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22		0x120
-		/* Remove the MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 as not used */
-	>;
-};
-
-&iomuxc {
-	pinctrl_captouch: captouchgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SPDIF_RX_GPIO5_IO4		0x16
-		>;
-	};
-
-	pinctrl_i2c2: i2c2grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_I2C2_SCL_I2C2_SCL		0x400001c3
-			MX8MN_IOMUXC_I2C2_SDA_I2C2_SDA		0x400001c3
-		>;
-	};
-
-	pinctrl_pca9534: pca9534grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7	0x16
-		>;
-	};
-
-	pinctrl_ptn5150: ptn5150grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_GPIO1_IO11_GPIO1_IO11	0x16
-		>;
-	};
-
-	pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SAI2_RXC_GPIO4_IO22	0x41
-		>;
-	};
-
-	pinctrl_uart1: uart1grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_UART1_RXD_UART1_DCE_RX	0x140
-			MX8MN_IOMUXC_UART1_TXD_UART1_DCE_TX	0x140
-		>;
-	};
-
-	pinctrl_uart3: uart3grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_UART3_RXD_UART3_DCE_RX	0x140
-			MX8MN_IOMUXC_UART3_TXD_UART3_DCE_TX	0x140
-		>;
-	};
-};
diff --git a/arch/arm/dts/imx8mn-var-som-u-boot.dtsi b/arch/arm/dts/imx8mn-var-som-u-boot.dtsi
new file mode 100644
index 00000000000..8f4e4efd8d9
--- /dev/null
+++ b/arch/arm/dts/imx8mn-var-som-u-boot.dtsi
@@ -0,0 +1,70 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2025 Dimonoff
+ */
+
+#include "imx8mn-u-boot.dtsi"
+
+/ {
+	aliases {
+		eeprom-som = &eeprom_som;
+	};
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b} {
+	bootph-pre-ram;
+};
+
+&{/soc@0/bus@30800000/i2c@30a20000/pmic@4b/regulators} {
+	bootph-pre-ram;
+};
+
+&eeprom_som {
+	bootph-all;
+	#address-cells = <1>;
+	#size-cells = <1>;
+	eth_mac_address: eth-mac-address@19 {
+		reg = <0x19 0x06>;
+	};
+};
+
+&fec1 {
+	nvmem-cells = <&eth_mac_address>;
+	nvmem-cell-names = "mac-address";
+};
+
+&gpio1 {
+	bootph-pre-ram;
+};
+
+&gpio2 {
+	bootph-pre-ram;
+};
+
+&gpio4 {
+	bootph-pre-ram;
+};
+
+&i2c1 {
+	bootph-all;
+};
+
+&usdhc3 {
+	bootph-pre-ram;
+};
+
+&pinctrl_i2c1 {
+	bootph-all;
+};
+
+&pinctrl_wdog {
+	bootph-pre-ram;
+};
+
+&pinctrl_pmic {
+	bootph-pre-ram;
+};
+
+&pinctrl_usdhc3 {
+	bootph-pre-ram;
+};
diff --git a/arch/arm/dts/imx8mn-var-som.dtsi b/arch/arm/dts/imx8mn-var-som.dtsi
deleted file mode 100644
index 4eb578a03fc..00000000000
--- a/arch/arm/dts/imx8mn-var-som.dtsi
+++ /dev/null
@@ -1,564 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright 2019 NXP
- * Copyright 2019-2020 Variscite Ltd.
- * Copyright (C) 2020 Krzysztof Kozlowski <[email protected]>
- */
-
-#include "imx8mn.dtsi"
-
-/ {
-	model = "Variscite VAR-SOM-MX8MN module";
-	compatible = "variscite,var-som-mx8mn", "fsl,imx8mn";
-
-	aliases {
-		eeprom-som = &eeprom_som;
-	};
-
-	chosen {
-		stdout-path = &uart4;
-	};
-
-	memory@40000000 {
-		device_type = "memory";
-		reg = <0x0 0x40000000 0 0x40000000>;
-	};
-
-	reg_eth_phy: regulator-eth-phy {
-		compatible = "regulator-fixed";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_reg_eth_phy>;
-		regulator-name = "eth_phy_pwr";
-		regulator-min-microvolt = <3300000>;
-		regulator-max-microvolt = <3300000>;
-		gpio = <&gpio2 9 GPIO_ACTIVE_HIGH>;
-		enable-active-high;
-	};
-};
-
-&A53_0 {
-	cpu-supply = <&buck2_reg>;
-};
-
-&A53_1 {
-	cpu-supply = <&buck2_reg>;
-};
-
-&A53_2 {
-	cpu-supply = <&buck2_reg>;
-};
-
-&A53_3 {
-	cpu-supply = <&buck2_reg>;
-};
-
-&ecspi1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_ecspi1>;
-	cs-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>,
-		   <&gpio1  0 GPIO_ACTIVE_LOW>;
-	/delete-property/ dmas;
-	/delete-property/ dma-names;
-	status = "okay";
-
-	/* Resistive touch controller */
-	touchscreen@0 {
-		reg = <0>;
-		compatible = "ti,ads7846";
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_restouch>;
-		interrupt-parent = <&gpio1>;
-		interrupts = <3 IRQ_TYPE_EDGE_FALLING>;
-
-		spi-max-frequency = <1500000>;
-		pendown-gpio = <&gpio1 3 GPIO_ACTIVE_LOW>;
-
-		ti,x-min = /bits/ 16 <125>;
-		touchscreen-size-x = <4008>;
-		ti,y-min = /bits/ 16 <282>;
-		touchscreen-size-y = <3864>;
-		ti,x-plate-ohms = /bits/ 16 <180>;
-		touchscreen-max-pressure = <255>;
-		touchscreen-average-samples = <10>;
-		ti,debounce-tol = /bits/ 16 <3>;
-		ti,debounce-rep = /bits/ 16 <1>;
-		ti,settle-delay-usec = /bits/ 16 <150>;
-		ti,keep-vref-on;
-		wakeup-source;
-	};
-};
-
-&fec1 {
-	pinctrl-names = "default", "sleep";
-	pinctrl-0 = <&pinctrl_fec1>;
-	pinctrl-1 = <&pinctrl_fec1_sleep>;
-	phy-mode = "rgmii";
-	phy-handle = <&ethphy>;
-	phy-supply = <&reg_eth_phy>;
-	fsl,magic-packet;
-	status = "okay";
-
-	mdio {
-		#address-cells = <1>;
-		#size-cells = <0>;
-
-		ethphy: ethernet-phy@4 { /* AR8033 or ADIN1300 */
-			compatible = "ethernet-phy-ieee802.3-c22";
-			reg = <4>;
-			reset-gpios = <&gpio1 9 GPIO_ACTIVE_LOW>;
-			reset-assert-us = <10000>;
-			/*
-			 * Deassert delay:
-			 * ADIN1300 requires 5ms.
-			 * AR8033   requires 1ms.
-			 */
-			reset-deassert-us = <20000>;
-		};
-	};
-};
-
-&i2c1 {
-	clock-frequency = <400000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c1>;
-	status = "okay";
-
-	pmic@4b {
-		compatible = "rohm,bd71847";
-		reg = <0x4b>;
-		pinctrl-names = "default";
-		pinctrl-0 = <&pinctrl_pmic>;
-		interrupt-parent = <&gpio2>;
-		interrupts = <8 IRQ_TYPE_LEVEL_LOW>;
-		rohm,reset-snvs-powered;
-
-		regulators {
-			buck1_reg: BUCK1 {
-				regulator-name = "buck1";
-				regulator-min-microvolt = <700000>;
-				regulator-max-microvolt = <1300000>;
-				regulator-boot-on;
-				regulator-always-on;
-				regulator-ramp-delay = <1250>;
-			};
-
-			buck2_reg: BUCK2 {
-				regulator-name = "buck2";
-				regulator-min-microvolt = <700000>;
-				regulator-max-microvolt = <1300000>;
-				regulator-boot-on;
-				regulator-always-on;
-				regulator-ramp-delay = <1250>;
-				rohm,dvs-run-voltage = <1000000>;
-				rohm,dvs-idle-voltage = <900000>;
-			};
-
-			buck3_reg: BUCK3 {
-				regulator-name = "buck3";
-				regulator-min-microvolt = <700000>;
-				regulator-max-microvolt = <1350000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			buck4_reg: BUCK4 {
-				regulator-name = "buck4";
-				regulator-min-microvolt = <2600000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			buck5_reg: BUCK5 {
-				regulator-name = "buck5";
-				regulator-min-microvolt = <1605000>;
-				regulator-max-microvolt = <1995000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			buck6_reg: BUCK6 {
-				regulator-name = "buck6";
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <1400000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			ldo1_reg: LDO1 {
-				regulator-name = "ldo1";
-				regulator-min-microvolt = <1600000>;
-				regulator-max-microvolt = <1900000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			ldo2_reg: LDO2 {
-				regulator-name = "ldo2";
-				regulator-min-microvolt = <800000>;
-				regulator-max-microvolt = <900000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			ldo3_reg: LDO3 {
-				regulator-name = "ldo3";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <3300000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-
-			ldo4_reg: LDO4 {
-				regulator-name = "ldo4";
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-always-on;
-			};
-
-			ldo5_reg: LDO5 {
-				regulator-compatible = "ldo5";
-				regulator-min-microvolt = <1800000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-always-on;
-			};
-
-			ldo6_reg: LDO6 {
-				regulator-name = "ldo6";
-				regulator-min-microvolt = <900000>;
-				regulator-max-microvolt = <1800000>;
-				regulator-boot-on;
-				regulator-always-on;
-			};
-		};
-	};
-
-	eeprom_som: eeprom@52 {
-		compatible = "atmel,24c04";
-		reg = <0x52>;
-		pagesize = <16>;
-	};
-};
-
-&i2c3 {
-	clock-frequency = <400000>;
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_i2c3>;
-	status = "okay";
-
-	/* TODO: configure audio, as of now just put a placeholder */
-	wm8904: codec@1a {
-		compatible = "wlf,wm8904";
-		reg = <0x1a>;
-		status = "disabled";
-	};
-};
-
-&snvs_pwrkey {
-	status = "okay";
-};
-
-/* Bluetooth */
-&uart2 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart2>;
-	assigned-clocks = <&clk IMX8MN_CLK_UART2>;
-	assigned-clock-parents = <&clk IMX8MN_SYS_PLL1_80M>;
-	uart-has-rtscts;
-	status = "okay";
-};
-
-/* Console */
-&uart4 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_uart4>;
-	status = "okay";
-};
-
-&usbotg1 {
-	dr_mode = "otg";
-	usb-role-switch;
-	status = "okay";
-};
-
-/* WIFI */
-&usdhc1 {
-	#address-cells = <1>;
-	#size-cells = <0>;
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc1>;
-	pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
-	bus-width = <4>;
-	non-removable;
-	keep-power-in-suspend;
-	status = "okay";
-
-	brcmf: bcrmf@1 {
-		reg = <1>;
-		compatible = "brcm,bcm4329-fmac";
-	};
-};
-
-/* SD */
-&usdhc2 {
-	assigned-clocks = <&clk IMX8MN_CLK_USDHC2>;
-	assigned-clock-rates = <200000000>;
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
-	pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
-	pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
-	cd-gpios = <&gpio1 10 GPIO_ACTIVE_LOW>;
-	bus-width = <4>;
-	vmmc-supply = <&reg_usdhc2_vmmc>;
-	status = "okay";
-};
-
-/* eMMC */
-&usdhc3 {
-	assigned-clocks = <&clk IMX8MN_CLK_USDHC3_ROOT>;
-	assigned-clock-rates = <400000000>;
-	pinctrl-names = "default", "state_100mhz", "state_200mhz";
-	pinctrl-0 = <&pinctrl_usdhc3>;
-	pinctrl-1 = <&pinctrl_usdhc3_100mhz>;
-	pinctrl-2 = <&pinctrl_usdhc3_200mhz>;
-	bus-width = <8>;
-	non-removable;
-	status = "okay";
-};
-
-&wdog1 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&pinctrl_wdog>;
-	fsl,ext-reset-output;
-	status = "okay";
-};
-
-&iomuxc {
-	pinctrl_ecspi1: ecspi1grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_ECSPI1_SCLK_ECSPI1_SCLK		0x13
-			MX8MN_IOMUXC_ECSPI1_MOSI_ECSPI1_MOSI		0x13
-			MX8MN_IOMUXC_ECSPI1_MISO_ECSPI1_MISO		0x13
-			MX8MN_IOMUXC_GPIO1_IO14_GPIO1_IO14		0x13
-			MX8MN_IOMUXC_GPIO1_IO00_GPIO1_IO0		0x13
-		>;
-	};
-
-	pinctrl_fec1: fec1grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_ENET_MDC_ENET1_MDC			0x3
-			MX8MN_IOMUXC_ENET_MDIO_ENET1_MDIO		0x3
-			MX8MN_IOMUXC_ENET_TD3_ENET1_RGMII_TD3		0x1f
-			MX8MN_IOMUXC_ENET_TD2_ENET1_RGMII_TD2		0x1f
-			MX8MN_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
-			MX8MN_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
-			MX8MN_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
-			MX8MN_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
-			MX8MN_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
-			MX8MN_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
-			MX8MN_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
-			MX8MN_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
-			MX8MN_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
-			MX8MN_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
-			MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x19
-		>;
-	};
-
-	pinctrl_fec1_sleep: fec1sleepgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_ENET_MDC_GPIO1_IO16		0x120
-			MX8MN_IOMUXC_ENET_MDIO_GPIO1_IO17		0x120
-			MX8MN_IOMUXC_ENET_TD3_GPIO1_IO18		0x120
-			MX8MN_IOMUXC_ENET_TD2_GPIO1_IO19		0x120
-			MX8MN_IOMUXC_ENET_TD1_GPIO1_IO20		0x120
-			MX8MN_IOMUXC_ENET_TD0_GPIO1_IO21		0x120
-			MX8MN_IOMUXC_ENET_RD3_GPIO1_IO29		0x120
-			MX8MN_IOMUXC_ENET_RD2_GPIO1_IO28		0x120
-			MX8MN_IOMUXC_ENET_RD1_GPIO1_IO27		0x120
-			MX8MN_IOMUXC_ENET_RD0_GPIO1_IO26		0x120
-			MX8MN_IOMUXC_ENET_TXC_GPIO1_IO23		0x120
-			MX8MN_IOMUXC_ENET_RXC_GPIO1_IO25		0x120
-			MX8MN_IOMUXC_ENET_RX_CTL_GPIO1_IO24		0x120
-			MX8MN_IOMUXC_ENET_TX_CTL_GPIO1_IO22		0x120
-			MX8MN_IOMUXC_GPIO1_IO09_GPIO1_IO9		0x120
-		>;
-	};
-
-	pinctrl_i2c1: i2c1grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_I2C1_SCL_I2C1_SCL		0x400001c3
-			MX8MN_IOMUXC_I2C1_SDA_I2C1_SDA		0x400001c3
-		>;
-	};
-
-	pinctrl_i2c3: i2c3grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_I2C3_SCL_I2C3_SCL		0x400001c3
-			MX8MN_IOMUXC_I2C3_SDA_I2C3_SDA		0x400001c3
-		>;
-	};
-
-	pinctrl_pmic: pmicirqgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SD1_DATA6_GPIO2_IO8	0x141
-		>;
-	};
-
-	pinctrl_reg_eth_phy: regethphygrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SD1_DATA7_GPIO2_IO9	0x41
-		>;
-	};
-
-	pinctrl_restouch: restouchgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_GPIO1_IO03_GPIO1_IO3	0x1c0
-		>;
-	};
-
-	pinctrl_uart2: uart2grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SAI3_TXFS_UART2_DCE_RX	0x140
-			MX8MN_IOMUXC_SAI3_TXC_UART2_DCE_TX	0x140
-			MX8MN_IOMUXC_SAI3_RXC_UART2_DCE_CTS_B	0x140
-			MX8MN_IOMUXC_SAI3_RXD_UART2_DCE_RTS_B	0x140
-		>;
-	};
-
-	pinctrl_uart4: uart4grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_UART4_RXD_UART4_DCE_RX	0x140
-			MX8MN_IOMUXC_UART4_TXD_UART4_DCE_TX	0x140
-		>;
-	};
-
-	pinctrl_usdhc1: usdhc1grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x190
-			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d0
-			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d0
-			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d0
-			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d0
-			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d0
-		>;
-	};
-
-	pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x194
-			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d4
-			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d4
-			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d4
-			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d4
-			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d4
-		>;
-	};
-
-	pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SD1_CLK_USDHC1_CLK		0x196
-			MX8MN_IOMUXC_SD1_CMD_USDHC1_CMD		0x1d6
-			MX8MN_IOMUXC_SD1_DATA0_USDHC1_DATA0	0x1d6
-			MX8MN_IOMUXC_SD1_DATA1_USDHC1_DATA1	0x1d6
-			MX8MN_IOMUXC_SD1_DATA2_USDHC1_DATA2	0x1d6
-			MX8MN_IOMUXC_SD1_DATA3_USDHC1_DATA3	0x1d6
-		>;
-	};
-
-	pinctrl_usdhc2_gpio: usdhc2gpiogrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_GPIO1_IO10_GPIO1_IO10	0x41
-		>;
-	};
-
-	pinctrl_usdhc2: usdhc2grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x190
-			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d0
-			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d0
-			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d0
-			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d0
-			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d0
-			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
-		>;
-	};
-
-	pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x194
-			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d4
-			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d4
-			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d4
-			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d4
-			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d4
-			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
-		>;
-	};
-
-	pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_SD2_CLK_USDHC2_CLK		0x196
-			MX8MN_IOMUXC_SD2_CMD_USDHC2_CMD		0x1d6
-			MX8MN_IOMUXC_SD2_DATA0_USDHC2_DATA0	0x1d6
-			MX8MN_IOMUXC_SD2_DATA1_USDHC2_DATA1	0x1d6
-			MX8MN_IOMUXC_SD2_DATA2_USDHC2_DATA2	0x1d6
-			MX8MN_IOMUXC_SD2_DATA3_USDHC2_DATA3	0x1d6
-			MX8MN_IOMUXC_GPIO1_IO04_USDHC2_VSELECT	0x1d0
-		>;
-	};
-
-	pinctrl_usdhc3: usdhc3grp {
-		fsl,pins = <
-			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x190
-			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d0
-			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d0
-			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d0
-			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d0
-			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d0
-			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d0
-			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d0
-			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d0
-			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d0
-			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x190
-		>;
-	};
-
-	pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x194
-			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d4
-			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d4
-			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d4
-			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d4
-			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d4
-			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d4
-			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d4
-			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d4
-			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d4
-			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x194
-		>;
-	};
-
-	pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_NAND_WE_B_USDHC3_CLK	0x196
-			MX8MN_IOMUXC_NAND_WP_B_USDHC3_CMD	0x1d6
-			MX8MN_IOMUXC_NAND_DATA04_USDHC3_DATA0	0x1d6
-			MX8MN_IOMUXC_NAND_DATA05_USDHC3_DATA1	0x1d6
-			MX8MN_IOMUXC_NAND_DATA06_USDHC3_DATA2	0x1d6
-			MX8MN_IOMUXC_NAND_DATA07_USDHC3_DATA3	0x1d6
-			MX8MN_IOMUXC_NAND_RE_B_USDHC3_DATA4	0x1d6
-			MX8MN_IOMUXC_NAND_CE2_B_USDHC3_DATA5	0x1d6
-			MX8MN_IOMUXC_NAND_CE3_B_USDHC3_DATA6	0x1d6
-			MX8MN_IOMUXC_NAND_CLE_USDHC3_DATA7	0x1d6
-			MX8MN_IOMUXC_NAND_CE1_B_USDHC3_STROBE	0x196
-		>;
-	};
-
-	pinctrl_wdog: wdoggrp {
-		fsl,pins = <
-			MX8MN_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B	0x166
-		>;
-	};
-};
diff --git a/arch/arm/dts/imx95-u-boot.dtsi b/arch/arm/dts/imx95-u-boot.dtsi
index 591cb317508..6dec159752b 100644
--- a/arch/arm/dts/imx95-u-boot.dtsi
+++ b/arch/arm/dts/imx95-u-boot.dtsi
@@ -96,6 +96,10 @@
 			};
 		};
 	};
+
+	imx95-cm7 {
+		compatible = "fsl,imx95-cm7";
+	};
 };
 
 &A55_0 {
diff --git a/arch/arm/mach-imx/ele_ahab.c b/arch/arm/mach-imx/ele_ahab.c
index 38e671e3935..4d4620dcafd 100644
--- a/arch/arm/mach-imx/ele_ahab.c
+++ b/arch/arm/mach-imx/ele_ahab.c
@@ -10,6 +10,7 @@
 #include <asm/mach-imx/ele_api.h>
 #include <asm/mach-imx/sys_proto.h>
 #include <asm/arch-imx/cpu.h>
+#include <asm/arch/imx-regs.h>
 #include <asm/arch/sys_proto.h>
 #include <console.h>
 #include <cpu_func.h>
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index d25e0910328..8b0d48b07b3 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -318,6 +318,7 @@ config TARGET_IMX8MN_VAR_SOM
 	select I2C_EEPROM
 	select DM_ETH_PHY
 	select NVMEM
+	imply OF_UPSTREAM
 
 config TARGET_KONTRON_PITX_IMX8M
 	bool "Support Kontron pITX-imx8m"
diff --git a/board/ge/common/vpd_reader.c b/board/ge/common/vpd_reader.c
index c28d2c03cfe..2422db38013 100644
--- a/board/ge/common/vpd_reader.c
+++ b/board/ge/common/vpd_reader.c
@@ -215,8 +215,8 @@ int read_i2c_vpd(struct vpd_cache *cache,
 
 	size = i2c_eeprom_size(dev);
 	if (size < 0) {
-		printf("Unable to get size of eeprom: %d\n", ret);
-		return ret;
+		printf("Unable to get size of eeprom: %d\n", size);
+		return size;
 	}
 
 	data = malloc(size);
diff --git a/board/nxp/imx8mm_evk/imx8mm_evk.c b/board/nxp/imx8mm_evk/imx8mm_evk.c
index ecc20768cb5..a8c1ef287e5 100644
--- a/board/nxp/imx8mm_evk/imx8mm_evk.c
+++ b/board/nxp/imx8mm_evk/imx8mm_evk.c
@@ -9,14 +9,11 @@
 #include <init.h>
 #include <miiphy.h>
 #include <netdev.h>
-#include <asm/global_data.h>
 
 #include <asm/arch/clock.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/io.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT)
 #define IMX_BOOT_IMAGE_GUID \
 	EFI_GUID(0xead2005e, 0x7780, 0x400b, 0x93, 0x48, \
diff --git a/board/nxp/imx8mn_evk/imx8mn_evk.c b/board/nxp/imx8mn_evk/imx8mn_evk.c
index 9d3f29f2253..e13b35c116a 100644
--- a/board/nxp/imx8mn_evk/imx8mn_evk.c
+++ b/board/nxp/imx8mn_evk/imx8mn_evk.c
@@ -3,12 +3,12 @@
  * Copyright 2019 NXP
  */
 
-#include <asm/arch/sys_proto.h>
-#include <asm/io.h>
 #include <config.h>
 #include <efi_loader.h>
 #include <env.h>
 #include <init.h>
+#include <asm/io.h>
+#include <asm/arch/sys_proto.h>
 
 #if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT)
 #define IMX_BOOT_IMAGE_GUID \
diff --git a/board/nxp/imx8mn_evk/spl.c b/board/nxp/imx8mn_evk/spl.c
index f96f5c45789..f07443e5c15 100644
--- a/board/nxp/imx8mn_evk/spl.c
+++ b/board/nxp/imx8mn_evk/spl.c
@@ -4,35 +4,21 @@
  *
  */
 
-#include <command.h>
-#include <cpu_func.h>
 #include <hang.h>
 #include <image.h>
 #include <init.h>
 #include <log.h>
 #include <spl.h>
-#include <asm/global_data.h>
-#include <asm/io.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/imx8mn_pins.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/mach-imx/boot_mode.h>
-#include <asm/arch/ddr.h>
-#include <asm/sections.h>
-
 #include <dm/uclass.h>
 #include <dm/device.h>
 #include <dm/uclass-internal.h>
 #include <dm/device-internal.h>
 #include <power/pmic.h>
 #include <power/pca9450.h>
-#include <asm/mach-imx/gpio.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <fsl_esdhc_imx.h>
-#include <mmc.h>
-
-DECLARE_GLOBAL_DATA_PTR;
+#include <asm/sections.h>
+#include <asm/arch/ddr.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
 
 int spl_board_boot_device(enum boot_device boot_dev_spl)
 {
diff --git a/board/nxp/imx8mp_evk/imx8mp_evk.c b/board/nxp/imx8mp_evk/imx8mp_evk.c
index 732c0fa561d..489e5ad4d43 100644
--- a/board/nxp/imx8mp_evk/imx8mp_evk.c
+++ b/board/nxp/imx8mp_evk/imx8mp_evk.c
@@ -3,10 +3,10 @@
  * Copyright 2019 NXP
  */
 
-#include <asm/arch/sys_proto.h>
 #include <config.h>
 #include <efi_loader.h>
 #include <env.h>
+#include <asm/arch/sys_proto.h>
 
 #if CONFIG_IS_ENABLED(EFI_HAVE_CAPSULE_SUPPORT)
 #define IMX_BOOT_IMAGE_GUID \
diff --git a/board/nxp/imx8mp_evk/spl.c b/board/nxp/imx8mp_evk/spl.c
index 12da1b2abfb..5b4aac42830 100644
--- a/board/nxp/imx8mp_evk/spl.c
+++ b/board/nxp/imx8mp_evk/spl.c
@@ -7,22 +7,13 @@
 #include <hang.h>
 #include <init.h>
 #include <log.h>
+#include <power/pmic.h>
+#include <power/pca9450.h>
 #include <spl.h>
-#include <asm/global_data.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/imx8mp_pins.h>
+#include <asm/arch/ddr.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/gpio.h>
-#include <asm/mach-imx/iomux-v3.h>
-#include <asm/mach-imx/mxc_i2c.h>
-#include <asm/arch/ddr.h>
-#include <power/pmic.h>
-#include <power/pca9450.h>
-#include <dm/uclass.h>
-#include <dm/device.h>
-
-DECLARE_GLOBAL_DATA_PTR;
 
 int spl_board_boot_device(enum boot_device boot_dev_spl)
 {
@@ -51,21 +42,6 @@ void spl_board_init(void)
 	puts("Normal Boot\n");
 }
 
-#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | PAD_CTL_PE)
-#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-struct i2c_pads_info i2c_pad_info1 = {
-	.scl = {
-		.i2c_mode = MX8MP_PAD_I2C1_SCL__I2C1_SCL | PC,
-		.gpio_mode = MX8MP_PAD_I2C1_SCL__GPIO5_IO14 | PC,
-		.gp = IMX_GPIO_NR(5, 14),
-	},
-	.sda = {
-		.i2c_mode = MX8MP_PAD_I2C1_SDA__I2C1_SDA | PC,
-		.gpio_mode = MX8MP_PAD_I2C1_SDA__GPIO5_IO15 | PC,
-		.gp = IMX_GPIO_NR(5, 15),
-	},
-};
-
 #if CONFIG_IS_ENABLED(DM_PMIC_PCA9450)
 int power_init_board(void)
 {
diff --git a/board/nxp/imx8mq_evk/spl.c b/board/nxp/imx8mq_evk/spl.c
index a346305c863..5116d806bb6 100644
--- a/board/nxp/imx8mq_evk/spl.c
+++ b/board/nxp/imx8mq_evk/spl.c
@@ -9,7 +9,6 @@
 #include <image.h>
 #include <init.h>
 #include <log.h>
-#include <asm/global_data.h>
 #include <asm/io.h>
 #include <errno.h>
 #include <asm/io.h>
@@ -30,8 +29,6 @@
 #include <spl.h>
 #include "../common/pfuze.h"
 
-DECLARE_GLOBAL_DATA_PTR;
-
 extern struct dram_timing_info dram_timing_b0;
 
 static void spl_dram_init(void)
diff --git a/board/nxp/imx8ulp_evk/imx8ulp_evk.c b/board/nxp/imx8ulp_evk/imx8ulp_evk.c
index 4bf77a488cc..cc34ecdec20 100644
--- a/board/nxp/imx8ulp_evk/imx8ulp_evk.c
+++ b/board/nxp/imx8ulp_evk/imx8ulp_evk.c
@@ -4,17 +4,11 @@
  */
 
 #include <env.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/arch/imx8ulp-pins.h>
+#include <asm/gpio.h>
 #include <asm/arch/clock.h>
+#include <asm/arch/imx8ulp-pins.h>
 #include <asm/arch/pcc.h>
 #include <asm/arch/sys_proto.h>
-#include <miiphy.h>
-#include <netdev.h>
-#include <asm/gpio.h>
-
-DECLARE_GLOBAL_DATA_PTR;
 
 #if IS_ENABLED(CONFIG_FEC_MXC)
 #define ENET_CLK_PAD_CTRL	(PAD_CTL_PUS_UP | PAD_CTL_DSE | PAD_CTL_IBE_ENABLE)
@@ -40,13 +34,6 @@ static int setup_fec(void)
 
 	return 0;
 }
-
-int board_phy_config(struct phy_device *phydev)
-{
-	if (phydev->drv->config)
-		phydev->drv->config(phydev);
-	return 0;
-}
 #endif
 
 #define I2C_PAD_CTRL	(PAD_CTL_ODE)
diff --git a/board/nxp/imx8ulp_evk/spl.c b/board/nxp/imx8ulp_evk/spl.c
index fe637077928..162b3a1a2e0 100644
--- a/board/nxp/imx8ulp_evk/spl.c
+++ b/board/nxp/imx8ulp_evk/spl.c
@@ -5,23 +5,13 @@
 
 #include <init.h>
 #include <spl.h>
-#include <asm/io.h>
-#include <errno.h>
+#include <asm/sections.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch/clock.h>
-#include <asm/arch/imx8ulp-pins.h>
-#include <dm/uclass.h>
-#include <dm/device.h>
-#include <dm/uclass-internal.h>
-#include <dm/device-internal.h>
-#include <dm/lists.h>
 #include <asm/arch/ddr.h>
 #include <asm/arch/rdc.h>
 #include <asm/arch/upower.h>
 #include <asm/mach-imx/ele_api.h>
-#include <asm/sections.h>
-
-DECLARE_GLOBAL_DATA_PTR;
 
 void spl_dram_init(void)
 {
diff --git a/board/nxp/imx93_frdm/imx93_frdm.c b/board/nxp/imx93_frdm/imx93_frdm.c
index cfbcde2e1a5..fb78a9bd036 100644
--- a/board/nxp/imx93_frdm/imx93_frdm.c
+++ b/board/nxp/imx93_frdm/imx93_frdm.c
@@ -7,7 +7,6 @@
 #include <efi_loader.h>
 #include <i2c.h>
 #include <init.h>
-#include <asm/global_data.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/arch-imx9/imx93_pins.h>
 #include <asm/arch/clock.h>
@@ -15,12 +14,10 @@
 #include <dm/device.h>
 #include <dm/uclass.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #if IS_ENABLED(CONFIG_EFI_HAVE_CAPSULE_SUPPORT)
 #define IMX_BOOT_IMAGE_GUID \
-	EFI_GUID(0xbc550d86, 0xda26, 0x4b70, 0xac, 0x05, \
-		 0x2a, 0x44, 0x8e, 0xda, 0x6f, 0x21)
+	EFI_GUID(0x6f86db61, 0xcda9, 0x489a, 0xbd, 0x36, \
+		 0x2f, 0x7c, 0x65, 0x1c, 0xa6, 0x5d)
 
 struct efi_fw_image fw_images[] = {
 	{
diff --git a/board/nxp/imx94_evk/imx94_evk.c b/board/nxp/imx94_evk/imx94_evk.c
index 588aa7548d4..2aeb21c1de7 100644
--- a/board/nxp/imx94_evk/imx94_evk.c
+++ b/board/nxp/imx94_evk/imx94_evk.c
@@ -9,12 +9,6 @@
 #include <asm/arch/clock.h>
 #include <asm/mach-imx/sys_proto.h>
 
-int board_early_init_f(void)
-{
-	init_uart_clk(0);
-	return 0;
-}
-
 int board_init(void)
 {
 	return 0;
diff --git a/board/nxp/imx94_evk/spl.c b/board/nxp/imx94_evk/spl.c
index 797806a8d4d..cc5b7f9ef0f 100644
--- a/board/nxp/imx94_evk/spl.c
+++ b/board/nxp/imx94_evk/spl.c
@@ -69,8 +69,6 @@ void board_init_f(ulong dummy)
 
 	arch_cpu_init();
 
-	board_early_init_f();
-
 	preloader_console_init();
 
 	debug("SOC: 0x%x\n", gd->arch.soc_rev);
diff --git a/board/nxp/imx95_evk/imx95_evk.c b/board/nxp/imx95_evk/imx95_evk.c
index ca1d916deab..620a69b53e5 100644
--- a/board/nxp/imx95_evk/imx95_evk.c
+++ b/board/nxp/imx95_evk/imx95_evk.c
@@ -7,14 +7,6 @@
 #include <asm/arch/clock.h>
 #include <asm/mach-imx/sys_proto.h>
 
-int board_early_init_f(void)
-{
-	/* UART1: A55, UART2: M33, UART3: M7 */
-	init_uart_clk(0);
-
-	return 0;
-}
-
 int board_late_init(void)
 {
 	if (IS_ENABLED(CONFIG_ENV_IS_IN_MMC))
diff --git a/board/nxp/imx95_evk/spl.c b/board/nxp/imx95_evk/spl.c
index 752d7f916b6..761a1a4a0f6 100644
--- a/board/nxp/imx95_evk/spl.c
+++ b/board/nxp/imx95_evk/spl.c
@@ -67,8 +67,6 @@ void board_init_f(ulong dummy)
 
 	arch_cpu_init();
 
-	board_early_init_f();
-
 	preloader_console_init();
 
 	debug("SOC: 0x%x\n", gd->arch.soc_rev);
diff --git a/board/toradex/smarc-imx95/smarc-imx95.c b/board/toradex/smarc-imx95/smarc-imx95.c
index c2cf872d9f9..6040c49975a 100644
--- a/board/toradex/smarc-imx95/smarc-imx95.c
+++ b/board/toradex/smarc-imx95/smarc-imx95.c
@@ -8,14 +8,6 @@
 
 #include "../common/tdx-cfg-block.h"
 
-int board_early_init_f(void)
-{
-	/* UART1: A55 */
-	init_uart_clk(0);
-
-	return 0;
-}
-
 int board_phys_sdram_size(phys_size_t *size)
 {
 	*size = PHYS_SDRAM_SIZE + PHYS_SDRAM_2_SIZE;
diff --git a/board/toradex/smarc-imx95/spl.c b/board/toradex/smarc-imx95/spl.c
index e0e39b8bb94..ce8da89410b 100644
--- a/board/toradex/smarc-imx95/spl.c
+++ b/board/toradex/smarc-imx95/spl.c
@@ -105,8 +105,6 @@ void board_init_f(ulong dummy)
 
 	arch_cpu_init();
 
-	board_early_init_f();
-
 	preloader_console_init();
 
 	debug("SOC: 0x%x\n", gd->arch.soc_rev);
diff --git a/board/variscite/imx8mn_var_som/Makefile b/board/variscite/imx8mn_var_som/Makefile
index 36d9c36dd2d..b75661ce271 100644
--- a/board/variscite/imx8mn_var_som/Makefile
+++ b/board/variscite/imx8mn_var_som/Makefile
@@ -4,9 +4,9 @@
 # SPDX-License-Identifier:      GPL-2.0+
 #
 
-obj-y += imx8mn_var_som.o
-
 ifdef CONFIG_XPL_BUILD
 obj-y += spl.o
 obj-y += ddr4_timing.o
+else
+obj-y += imx8mn_var_som.o
 endif
diff --git a/board/variscite/imx8mn_var_som/imx8mn_var_som.c b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
index 14aa93c527b..945f389cdd9 100644
--- a/board/variscite/imx8mn_var_som/imx8mn_var_som.c
+++ b/board/variscite/imx8mn_var_som/imx8mn_var_som.c
@@ -49,8 +49,6 @@ int board_mmc_get_env_dev(int devno)
 	return devno;
 }
 
-#if !defined(CONFIG_XPL_BUILD)
-
 #if defined(CONFIG_DISPLAY_BOARDINFO)
 
 static void display_som_infos(struct var_imx8_eeprom_info *info)
@@ -221,5 +219,3 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 	return configure_phy_reset_gpios(blob);
 }
 #endif /* CONFIG_OF_BOARD_SETUP */
-
-#endif /* CONFIG_XPL_BUILD */
diff --git a/board/variscite/imx8mn_var_som/spl.c b/board/variscite/imx8mn_var_som/spl.c
index 01a63c69641..483e9be400d 100644
--- a/board/variscite/imx8mn_var_som/spl.c
+++ b/board/variscite/imx8mn_var_som/spl.c
@@ -9,12 +9,9 @@
 #include <spl.h>
 #include <asm/arch/clock.h>
 #include <asm/arch/ddr.h>
-#include <asm/arch/imx8mn_pins.h>
 #include <asm/arch/sys_proto.h>
 #include <asm/mach-imx/boot_mode.h>
-#include <asm/mach-imx/gpio.h>
 #include <asm/sections.h>
-#include <dm/device.h>
 #include <dm/uclass.h>
 
 int spl_board_boot_device(enum boot_device boot_dev_spl)
@@ -41,13 +38,6 @@ void spl_board_init(void)
 		puts("Failed to find clock node. Check device tree\n");
 }
 
-int board_early_init_f(void)
-{
-	init_uart_clk(3);
-
-	return 0;
-}
-
 void board_init_f(ulong dummy)
 {
 	int ret;
@@ -57,8 +47,6 @@ void board_init_f(ulong dummy)
 
 	arch_cpu_init();
 
-	board_early_init_f();
-
 	timer_init();
 
 	ret = spl_init();
diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig
index b9f3b9b8999..95c442389d0 100644
--- a/configs/imx8mn_var_som_defconfig
+++ b/configs/imx8mn_var_som_defconfig
@@ -9,7 +9,7 @@ CONFIG_NR_DRAM_BANKS=1
 CONFIG_ENV_SIZE=0x2000
 CONFIG_ENV_OFFSET=0xFFFFDE00
 CONFIG_DM_GPIO=y
-CONFIG_DEFAULT_DEVICE_TREE="imx8mn-var-som-symphony"
+CONFIG_DEFAULT_DEVICE_TREE="freescale/imx8mn-var-som-symphony"
 CONFIG_TARGET_IMX8MN_VAR_SOM=y
 CONFIG_OF_LIBFDT_OVERLAY=y
 CONFIG_SYS_MONITOR_LEN=524288
diff --git a/configs/imx943_evk_defconfig b/configs/imx943_evk_defconfig
index 0371dbe28a9..ef4f9a8fcbc 100644
--- a/configs/imx943_evk_defconfig
+++ b/configs/imx943_evk_defconfig
@@ -37,7 +37,6 @@ CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd"
 CONFIG_DEFAULT_FDT_FILE="imx943-evk.dtb"
 CONFIG_SYS_CBSIZE=2048
 CONFIG_SYS_PBSIZE=2074
-CONFIG_BOARD_EARLY_INIT_F=y
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_PCI_INIT_R=y
 CONFIG_SPL_MAX_SIZE=0x30000
diff --git a/configs/imx95_15x15_evk_defconfig b/configs/imx95_15x15_evk_defconfig
index f3099f14401..38a855417d0 100644
--- a/configs/imx95_15x15_evk_defconfig
+++ b/configs/imx95_15x15_evk_defconfig
@@ -38,7 +38,6 @@ CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd"
 CONFIG_DEFAULT_FDT_FILE="imx95-15x15-evk.dtb"
 CONFIG_SYS_CBSIZE=2048
 CONFIG_SYS_PBSIZE=2074
-CONFIG_BOARD_EARLY_INIT_F=y
 # CONFIG_BOARD_INIT is not set
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_PCI_INIT_R=y
@@ -71,6 +70,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EFIDEBUG=y
@@ -104,6 +104,8 @@ CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_SPL_FIRMWARE=y
 # CONFIG_SCMI_AGENT_SMCCC is not set
+CONFIG_IMX_SM_CPU=y
+CONFIG_IMX_SM_LMM=y
 CONFIG_IMX_RGPIO2P=y
 CONFIG_DM_PCA953X=y
 CONFIG_ADP5585_GPIO=y
@@ -137,6 +139,7 @@ CONFIG_SPL_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SPL_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REMOTEPROC_IMX=y
 CONFIG_DM_RTC=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
diff --git a/configs/imx95_evk.config b/configs/imx95_evk.config
index 631ec23c335..3db583cce59 100644
--- a/configs/imx95_evk.config
+++ b/configs/imx95_evk.config
@@ -37,7 +37,6 @@ CONFIG_BOOTCOMMAND="bootflow scan -l; run bsp_bootcmd"
 CONFIG_DEFAULT_FDT_FILE="imx95-19x19-evk.dtb"
 CONFIG_SYS_CBSIZE=2048
 CONFIG_SYS_PBSIZE=2074
-CONFIG_BOARD_EARLY_INIT_F=y
 # CONFIG_BOARD_INIT is not set
 CONFIG_BOARD_LATE_INIT=y
 CONFIG_PCI_INIT_R=y
@@ -69,6 +68,7 @@ CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
 CONFIG_CMD_PCI=y
 CONFIG_CMD_POWEROFF=y
+CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_SNTP=y
 CONFIG_CMD_CACHE=y
 CONFIG_CMD_EFIDEBUG=y
@@ -105,6 +105,8 @@ CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_SPL_FIRMWARE=y
 # CONFIG_SCMI_AGENT_SMCCC is not set
+CONFIG_IMX_SM_CPU=y
+CONFIG_IMX_SM_LMM=y
 CONFIG_IMX_RGPIO2P=y
 CONFIG_DM_PCA953X=y
 CONFIG_ADP5585_GPIO=y
@@ -139,6 +141,7 @@ CONFIG_SPL_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_SPL_DM_REGULATOR_FIXED=y
 CONFIG_DM_REGULATOR_GPIO=y
+CONFIG_REMOTEPROC_IMX=y
 CONFIG_DM_RTC=y
 CONFIG_DM_SERIAL=y
 CONFIG_FSL_LPUART=y
diff --git a/configs/toradex-smarc-imx95_defconfig b/configs/toradex-smarc-imx95_defconfig
index 5ab420ae519..77b355c12d6 100644
--- a/configs/toradex-smarc-imx95_defconfig
+++ b/configs/toradex-smarc-imx95_defconfig
@@ -43,7 +43,6 @@ CONFIG_SYS_PBSIZE=2074
 CONFIG_LOG=y
 # CONFIG_DISPLAY_BOARDINFO is not set
 CONFIG_DISPLAY_BOARDINFO_LATE=y
-CONFIG_BOARD_EARLY_INIT_F=y
 # CONFIG_BOARD_INIT is not set
 CONFIG_SPL_MAX_SIZE=0x30000
 CONFIG_SPL_BOARD_INIT=y
diff --git a/doc/board/nxp/rproc.rst b/doc/board/nxp/rproc.rst
index b023c1fadf6..7836935bbc7 100644
--- a/doc/board/nxp/rproc.rst
+++ b/doc/board/nxp/rproc.rst
@@ -67,3 +67,16 @@ corresponding board.
     rproc load 0 0x90000000 ${filesize}
 
     rproc start 0
+
+i.MX95-EVK
+-------------------
+
+Steps to start the Cortex-M7 core, need to choose the correct file for
+corresponding board. The example is for i.MX95 15x15 EVK, use imx95-19x19-evk
+if your board is i.MX95 19x19 EVK.
+
+    load mmc 1:2 ${loadaddr} /lib/firmware/imx95-15x15-evk_m7_TCM_rpmsg_lite_str_echo_rtos.elf
+
+    rproc load 0 ${loadaddr} ${filesize}
+
+    rproc start 0
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index 4fda1b0c28c..eb6a1cab565 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -423,7 +423,7 @@ config FEC_MXC_MDIO_BASE
 
 config FEC_MXC
 	bool "FEC Ethernet controller"
-	depends on MX28 || MX5 || MX6 || MX7 || IMX8 || IMX8M || IMX8ULP || IMX93 || VF610
+	depends on MX28 || MX5 || MX6 || MX7 || IMX8 || IMX8M || IMX8ULP || IMX91 || IMX93 || VF610
 	help
 	  This driver supports the 10/100 Fast Ethernet controller for
 	  NXP i.MX processors.
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c
index fee9973c4dc..1c51e936b5b 100644
--- a/drivers/net/fec_mxc.c
+++ b/drivers/net/fec_mxc.c
@@ -594,7 +594,7 @@ static int fecmxc_init(struct udevice *dev)
 
 	/* Do not access reserved register */
 	if (!is_mx6ul() && !is_mx6ull() && !is_imx8() && !is_imx8m() && !is_imx8ulp() &&
-	    !is_imx93()) {
+	    !is_imx91() && !is_imx93()) {
 		/* clear MIB RAM */
 		for (i = mib_ptr; i <= mib_ptr + 0xfc; i += 4)
 			writel(0, i);
@@ -1236,7 +1236,7 @@ static int fecmxc_set_ref_clk(struct clk *clk_ref, phy_interface_t interface)
 		 interface == PHY_INTERFACE_MODE_RGMII_RXID ||
 		 interface == PHY_INTERFACE_MODE_RGMII_TXID) {
 		freq = 125000000;
-		if (is_imx93())
+		if (is_imx91() || is_imx93())
 			freq = freq << 1;
 	} else {
 		return -EINVAL;
diff --git a/drivers/remoteproc/imx_rproc.c b/drivers/remoteproc/imx_rproc.c
index 9bb55327998..3f8cea127ec 100644
--- a/drivers/remoteproc/imx_rproc.c
+++ b/drivers/remoteproc/imx_rproc.c
@@ -11,6 +11,7 @@
 #include <linux/types.h>
 #include <regmap.h>
 #include <remoteproc.h>
+#include <scmi_nxp_protocols.h>
 #include <syscon.h>
 
 #include "imx_rproc.h"
@@ -37,15 +38,32 @@
 #define IMX_SIP_RPROC_STARTED		0x01
 #define IMX_SIP_RPROC_STOP		0x02
 
+/* Must align with System Manager Firmware */
+#define IMX95_M7_CPUID			1
+#define IMX95_M7_LMID			1
+
+/* Logical Machine API Operation */
+#define IMX_RPROC_FLAGS_SM_LMM_OP	BIT(0)
+/* CPU API Operation */
+#define IMX_RPROC_FLAGS_SM_CPU_OP	BIT(1)
+/* Linux has permission to handle the Logical Machine of remote cores */
+#define IMX_RPROC_FLAGS_SM_LMM_AVAIL	BIT(2)
+
 struct imx_rproc {
 	const struct imx_rproc_dcfg	*dcfg;
 	struct regmap *regmap;
+	u32				flags;
+	/* For System Manager based system */
+	struct udevice			*lmm_dev;
+	struct udevice			*cpu_dev;
+	ulong				reset_vector;
 };
 
 /* att flags: lower 16 bits specifying core, higher 16 bits for flags  */
 /* M4 own area. Can be mapped at probe */
 #define ATT_OWN         BIT(31)
 #define ATT_IOMEM       BIT(30)
+#define ATT_ECC         BIT(29)
 
 static int imx_rproc_arm_smc_start(struct udevice *dev)
 {
@@ -64,6 +82,41 @@ static int imx_rproc_mmio_start(struct udevice *dev)
 	return regmap_update_bits(priv->regmap, dcfg->src_reg, dcfg->src_mask, dcfg->src_start);
 }
 
+static int imx_rproc_sm_start(struct udevice *dev)
+{
+	struct imx_rproc *priv = dev_get_priv(dev);
+	const struct imx_rproc_dcfg *dcfg = priv->dcfg;
+	int ret;
+
+	if (priv->flags & IMX_RPROC_FLAGS_SM_CPU_OP) {
+		ret = scmi_imx_cpu_reset_vector_set(priv->cpu_dev, dcfg->cpuid, 0,
+						    priv->reset_vector, true, false, false);
+		if (ret) {
+			dev_err(dev, "Failed to set reset vector cpuid(%u): %d\n",
+				dcfg->cpuid, ret);
+			return ret;
+		}
+
+		return scmi_imx_cpu_start(priv->cpu_dev, dcfg->cpuid, true);
+	}
+
+	ret = scmi_imx_lmm_reset_vector_set(priv->lmm_dev, dcfg->lmid, dcfg->cpuid, 0,
+					    priv->reset_vector);
+	if (ret) {
+		dev_err(dev, "Failed to set reset vector lmid(%u), cpuid(%u): %d\n",
+			dcfg->lmid, dcfg->cpuid, ret);
+		return ret;
+	}
+
+	ret = scmi_imx_lmm_power_boot(priv->lmm_dev, dcfg->lmid, true);
+	if (ret) {
+		dev_err(dev, "Failed to boot lmm(%d): %d\n", ret, dcfg->lmid);
+		return ret;
+	}
+
+	return 0;
+}
+
 static int imx_rproc_start(struct udevice *dev)
 {
 	struct imx_rproc *priv = dev_get_priv(dev);
@@ -99,6 +152,17 @@ static int imx_rproc_mmio_stop(struct udevice *dev)
 	return regmap_update_bits(priv->regmap, dcfg->src_reg, dcfg->src_mask, dcfg->src_stop);
 }
 
+static int imx_rproc_sm_stop(struct udevice *dev)
+{
+	struct imx_rproc *priv = dev_get_priv(dev);
+	const struct imx_rproc_dcfg *dcfg = priv->dcfg;
+
+	if (priv->flags & IMX_RPROC_FLAGS_SM_CPU_OP)
+		return scmi_imx_cpu_start(priv->cpu_dev, dcfg->cpuid, false);
+
+	return scmi_imx_lmm_shutdown(priv->lmm_dev, dcfg->lmid, 0);
+}
+
 static int imx_rproc_stop(struct udevice *dev)
 {
 	struct imx_rproc *priv = dev_get_priv(dev);
@@ -145,6 +209,20 @@ static int imx_rproc_mmio_is_running(struct udevice *dev)
 	return 1;
 }
 
+static int imx_rproc_sm_is_running(struct udevice *dev)
+{
+	struct imx_rproc *priv = dev_get_priv(dev);
+	const struct imx_rproc_dcfg *dcfg = priv->dcfg;
+	int ret;
+	bool started = false;
+
+	ret = scmi_imx_cpu_started(priv->cpu_dev, dcfg->cpuid, &started);
+	if (ret || !started)
+		return 1;
+
+	return 0;
+}
+
 static int imx_rproc_is_running(struct udevice *dev)
 {
 	struct imx_rproc *priv = dev_get_priv(dev);
@@ -202,6 +280,34 @@ static void *imx_rproc_device_to_virt(struct udevice *dev, ulong da, ulong size,
 
 static int imx_rproc_load(struct udevice *dev, ulong addr, ulong size)
 {
+	struct imx_rproc *priv = dev_get_priv(dev);
+	const struct imx_rproc_dcfg *dcfg = priv->dcfg;
+	int i;
+
+	if (IS_ENABLED(CONFIG_IMX_SM_LMM)) {
+		if (!(priv->flags & (IMX_RPROC_FLAGS_SM_LMM_AVAIL | IMX_RPROC_FLAGS_SM_CPU_OP)))
+			return -EACCES;
+	}
+
+	/* Only used for SM based System */
+	priv->reset_vector = rproc_elf_get_boot_addr(dev, addr) & GENMASK(31, 16);
+
+	/*
+	 * Before loading elf, need do ECC initialization by clearing the memory
+	 * region, if ATT_ECC is set.
+	 */
+	for (i = 0; i < dcfg->att_size; i++) {
+		const struct imx_rproc_att *att = &dcfg->att[i];
+
+		if (!(att->flags & ATT_ECC))
+			continue;
+
+		if (att->flags & ATT_IOMEM)
+			memset_io((void __iomem *)(long)att->sa, 0, att->size);
+		else
+			memset((void *)(long)att->sa, 0, att->size);
+	}
+
 	return rproc_elf_load_image(dev, addr, size);
 }
 
@@ -218,19 +324,65 @@ static int imx_rproc_probe(struct udevice *dev)
 {
 	struct imx_rproc *priv = dev_get_priv(dev);
 	struct imx_rproc_dcfg *dcfg = (struct imx_rproc_dcfg *)dev_get_driver_data(dev);
+	struct scmi_imx_lmm_info info;
 	ofnode node;
+	int ret;
 
 	node = dev_ofnode(dev);
 
 	priv->dcfg = dcfg;
 
-	if (dcfg->method != IMX_RPROC_MMIO)
+	if (dcfg->method == IMX_RPROC_MMIO) {
+		priv->regmap = syscon_regmap_lookup_by_phandle(dev, "syscon");
+		if (IS_ERR(priv->regmap)) {
+			dev_err(dev, "No syscon: %ld\n", PTR_ERR(priv->regmap));
+			return PTR_ERR(priv->regmap);
+		}
 		return 0;
+	} else {
+		if (IS_ENABLED(CONFIG_IMX_SM_LMM)) {
+			struct udevice *lmm_dev;
+
+			ret = uclass_get_device_by_name(UCLASS_SCMI_BASE, "protocol@80", &lmm_dev);
+			if (ret) {
+				dev_err(dev, "Failed to get SM LMM protocol dev\n");
+				return ret;
+			}
+
+			priv->lmm_dev = lmm_dev;
 
-	priv->regmap = syscon_regmap_lookup_by_phandle(dev, "syscon");
-	if (IS_ERR(priv->regmap)) {
-		dev_err(dev, "No syscon: %ld\n", PTR_ERR(priv->regmap));
-		return PTR_ERR(priv->regmap);
+			ret = scmi_imx_lmm_info(lmm_dev, LMM_ID_DISCOVER, &info);
+			if (ret) {
+				dev_err(dev, "Failed to get lmm info\n");
+				return ret;
+			}
+
+			if (dcfg->lmid != info.lmid) {
+				ret = scmi_imx_lmm_power_boot(lmm_dev, dcfg->lmid, false);
+				if (ret == -EACCES) {
+					dev_err(dev, "Remoteproc not under U-boot control: only support detect running\n");
+				} else if (ret) {
+					dev_err(dev, "power on lmm fail:%d\n", ret);
+					return ret;
+				} else {
+					priv->flags |= IMX_RPROC_FLAGS_SM_LMM_AVAIL;
+				}
+			} else {
+				priv->flags |= IMX_RPROC_FLAGS_SM_CPU_OP;
+			}
+		}
+
+		if (IS_ENABLED(CONFIG_IMX_SM_CPU)) {
+			struct udevice *cpu_dev;
+
+			ret = uclass_get_device_by_name(UCLASS_SCMI_BASE, "protocol@82", &cpu_dev);
+			if (ret) {
+				dev_err(dev, "Failed to get SM LMM protocol dev\n");
+				return ret;
+			}
+
+			priv->cpu_dev = cpu_dev;
+		}
 	}
 
 	return 0;
@@ -351,12 +503,39 @@ static const struct imx_rproc_dcfg imx_rproc_cfg_imx93 = {
 	.ops		= &imx_rproc_ops_arm_smc,
 };
 
+static const struct imx_rproc_att imx_rproc_att_imx95_m7[] = {
+	/* dev addr , sys addr  , size	    , flags */
+	/* TCM CODE NON-SECURE */
+	{ 0x00000000, 0x203C0000, 0x00040000, ATT_OWN | ATT_IOMEM | ATT_ECC },
+
+	/* TCM SYS NON-SECURE*/
+	{ 0x20000000, 0x20400000, 0x00040000, ATT_OWN | ATT_IOMEM | ATT_ECC },
+
+	/* DDR */
+	{ 0x80000000, 0x80000000, 0x50000000, 0 },
+};
+
+static const struct imx_rproc_plat_ops imx_rproc_ops_sm = {
+	.start		= imx_rproc_sm_start,
+	.stop		= imx_rproc_sm_stop,
+	.is_running	= imx_rproc_sm_is_running,
+};
+
+static const struct imx_rproc_dcfg imx_rproc_cfg_imx95_m7 = {
+	.att		= imx_rproc_att_imx95_m7,
+	.att_size	= ARRAY_SIZE(imx_rproc_att_imx95_m7),
+	.ops		= &imx_rproc_ops_sm,
+	.cpuid		= IMX95_M7_CPUID,
+	.lmid		= IMX95_M7_LMID,
+};
+
 static const struct udevice_id imx_rproc_ids[] = {
 	{ .compatible = "fsl,imx8mm-cm4", .data = (ulong)&imx_rproc_cfg_imx8mq },
 	{ .compatible = "fsl,imx8mn-cm7", .data = (ulong)&imx_rproc_cfg_imx8mn, },
 	{ .compatible = "fsl,imx8mp-cm7", .data = (ulong)&imx_rproc_cfg_imx8mn, },
 	{ .compatible = "fsl,imx8mq-cm4", .data = (ulong)&imx_rproc_cfg_imx8mq },
 	{ .compatible = "fsl,imx93-cm33", .data = (ulong)&imx_rproc_cfg_imx93 },
+	{ .compatible = "fsl,imx95-cm7", .data = (ulong)&imx_rproc_cfg_imx95_m7 },
 	{}
 };
 
diff --git a/drivers/remoteproc/imx_rproc.h b/drivers/remoteproc/imx_rproc.h
index 7a82dc4a195..1629bc7f6e7 100644
--- a/drivers/remoteproc/imx_rproc.h
+++ b/drivers/remoteproc/imx_rproc.h
@@ -51,6 +51,9 @@ struct imx_rproc_dcfg {
 	enum imx_rproc_method		method;
 	u32				flags;
 	const struct imx_rproc_plat_ops	*ops;
+	/* For System Manager(SM) based SoCs, the IDs are from SM firmware */
+	u32				cpuid;
+	u32				lmid;
 };
 
 #endif /* _IMX_RPROC_H */