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authorVenkatesh Yadav Abbarapu <[email protected]>2025-04-30 10:39:23 +0530
committerMichal Simek <[email protected]>2026-03-23 14:58:46 +0100
commit79a647c6b7d2a52108bbc2cf8dce2eeb6198f025 (patch)
treee045bc0ea91dbb87e2472e95ab0990a51fdffe8c
parentc82aedd185933493a2926c519e2dc8d5f3998440 (diff)
spi: cadence_qspi: Disable the DAC mode in indirect read
Hang has been observed on QEMU, as it starts with indac read and fills sram, but after dma is triggered, it tries dac read instead (based on priority) which gets blocked. Disable the DAC mode in indirect DMA read and enable back for writes as DAC mode is used. Signed-off-by: Venkatesh Yadav Abbarapu <[email protected]> Tested-by: Padmarao Begari <[email protected]> Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/[email protected]
-rw-r--r--drivers/spi/cadence_ospi_versal.c7
1 files changed, 7 insertions, 0 deletions
diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c
index a00642d09d3..e6f4ba49e77 100644
--- a/drivers/spi/cadence_ospi_versal.c
+++ b/drivers/spi/cadence_ospi_versal.c
@@ -35,6 +35,10 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
bytes_to_dma = n_rx - rx_rem;
if (bytes_to_dma) {
+ if (priv->use_dac_mode)
+ clrbits_le32(priv->regbase + CQSPI_REG_CONFIG,
+ CQSPI_REG_CONFIG_DIRECT);
+
cadence_qspi_apb_enable_linear_mode(false);
reg = readl(priv->regbase + CQSPI_REG_CONFIG);
reg |= CQSPI_REG_CONFIG_ENBL_DMA;
@@ -125,6 +129,9 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv,
memcpy(rxbuf, rxbuf + 1, n_rx - 1);
}
+ if (priv->use_dac_mode)
+ cadence_qspi_apb_dac_mode_enable(priv->regbase);
+
return 0;
}