diff options
| author | Julien Stephan <[email protected]> | 2026-07-15 16:28:54 +0200 |
|---|---|---|
| committer | David Lechner <[email protected]> | 2026-07-29 10:10:10 -0500 |
| commit | 7a26bf29e26e2d18829435fbd7c7adf8d560468d (patch) | |
| tree | 21dd2192fdc0b096725bdf5991f669534083bcf3 | |
| parent | 8ee35039efae8ee9e1f9645d16c0211473920a0f (diff) | |
clk: mediatek: mt8365: use driver data to store the clock tree
Pass each controller's struct mtk_clk_tree through the driver data and use
the generic probe function for all the MT8365 clock drivers, instead of a
dedicated probe per controller.
The apmixedsys and topckgen controllers keep their own U_BOOT_DRIVER since
they rely on dedicated ops and on the parent bind() callback, but they now
get their tree from the compatible data.
No functional change intended.
Signed-off-by: Julien Stephan <[email protected]>
Link: https://patch.msgid.link/20260715-b4-mtk-clk-cleanup-clock-gate-drivers-v2-26-23e907516010@baylibre.com
Signed-off-by: David Lechner <[email protected]>
| -rw-r--r-- | drivers/clk/mediatek/clk-mt8365.c | 24 |
1 files changed, 10 insertions, 14 deletions
diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c index 1a0d1149496..ef0d7cc9828 100644 --- a/drivers/clk/mediatek/clk-mt8365.c +++ b/drivers/clk/mediatek/clk-mt8365.c @@ -761,16 +761,6 @@ static const struct mtk_clk_tree mt8365_infracfg_tree = { .num_gates = ARRAY_SIZE(ifr_clks), }; -static int mt8365_apmixedsys_probe(struct udevice *dev) -{ - return mtk_common_clk_init(dev, &mt8365_apmixed_tree); -} - -static int mt8365_topckgen_probe(struct udevice *dev) -{ - return mtk_common_clk_init(dev, &mt8365_topckgen_tree); -} - static int mt8365_clk_probe(struct udevice *dev) { const struct mtk_clk_tree *tree = (void *)dev_get_driver_data(dev); @@ -779,12 +769,18 @@ static int mt8365_clk_probe(struct udevice *dev) } static const struct udevice_id mt8365_apmixed_compat[] = { - { .compatible = "mediatek,mt8365-apmixedsys", }, + { + .compatible = "mediatek,mt8365-apmixedsys", + .data = (ulong)&mt8365_apmixed_tree, + }, { } }; static const struct udevice_id mt8365_topckgen_compat[] = { - { .compatible = "mediatek,mt8365-topckgen", }, + { + .compatible = "mediatek,mt8365-topckgen", + .data = (ulong)&mt8365_topckgen_tree, + }, { } }; @@ -801,7 +797,7 @@ U_BOOT_DRIVER(mt8365_clk_apmixedsys) = { .id = UCLASS_CLK, .of_match = mt8365_apmixed_compat, .bind = mtk_common_clk_parent_bind, - .probe = mt8365_apmixedsys_probe, + .probe = mt8365_clk_probe, .priv_auto = sizeof(struct mtk_clk_priv), .ops = &mtk_clk_apmixedsys_ops, .flags = DM_FLAG_PRE_RELOC, @@ -812,7 +808,7 @@ U_BOOT_DRIVER(mt8365_clk_topckgen) = { .id = UCLASS_CLK, .of_match = mt8365_topckgen_compat, .bind = mtk_common_clk_parent_bind, - .probe = mt8365_topckgen_probe, + .probe = mt8365_clk_probe, .priv_auto = sizeof(struct mtk_clk_priv), .ops = &mtk_clk_topckgen_ops, .flags = DM_FLAG_PRE_RELOC, |