diff options
| author | Marek Vasut <[email protected]> | 2021-09-14 05:22:31 +0200 |
|---|---|---|
| committer | Jagan Teki <[email protected]> | 2021-12-02 11:10:40 +0530 |
| commit | 846d1d9c119b9046fa120a76e6d01192fa74ad52 (patch) | |
| tree | d0ff08f8f2d1621b77432f10beecf33523fb3093 | |
| parent | 4a14bfffd42f968ed9d72a780a8d44a9053c5b95 (diff) | |
mtd: cqspi: Wait for transfer completion
Wait for the read/write transfer finish bit get actually cleared,
this does not happen immediately on at least SoCFPGA Gen5.
Signed-off-by: Marek Vasut <[email protected]>
Reviewed-by: Jagan Teki <[email protected]>
Cc: Vignesh R <[email protected]>
Cc: Pratyush Yadav <[email protected]>
| -rw-r--r-- | drivers/spi/cadence_qspi_apb.c | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 429ee335db6..2cdf4c9c9f8 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -858,6 +858,14 @@ cadence_qspi_apb_indirect_read_execute(struct cadence_spi_plat *plat, writel(CQSPI_REG_INDIRECTRD_DONE, plat->regbase + CQSPI_REG_INDIRECTRD); + /* Check indirect done status */ + ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTRD, + CQSPI_REG_INDIRECTRD_DONE, 0, 10, 0); + if (ret) { + printf("Indirect read clear completion error (%i)\n", ret); + goto failrd; + } + return 0; failrd: @@ -1012,6 +1020,15 @@ cadence_qspi_apb_indirect_write_execute(struct cadence_spi_plat *plat, /* Clear indirect completion status */ writel(CQSPI_REG_INDIRECTWR_DONE, plat->regbase + CQSPI_REG_INDIRECTWR); + + /* Check indirect done status */ + ret = wait_for_bit_le32(plat->regbase + CQSPI_REG_INDIRECTWR, + CQSPI_REG_INDIRECTWR_DONE, 0, 10, 0); + if (ret) { + printf("Indirect write clear completion error (%i)\n", ret); + goto failwr; + } + if (bounce_buf) free(bounce_buf); return 0; |