diff options
| author | Yao Zi <[email protected]> | 2025-05-30 09:48:48 +0000 |
|---|---|---|
| committer | Leo Yu-Chi Liang <[email protected]> | 2025-06-09 10:44:06 +0800 |
| commit | 85cfabe895f4f32a5b65c114ebef7793321d5e01 (patch) | |
| tree | 89c18fa8563ab8076b047a1d81300dc812d613b5 | |
| parent | 0463545678883b8d2b417eea08c76d47396104b7 (diff) | |
riscv: cpu: th1520: Support cache enabling/disabling in M mode only
These operations rely on a customized M-mode CSR, MHCR, which isn't
available when running in S mode.
Let's fallback to the generic weak stub when running in S mode to avoid
illegal accesses.
Signed-off-by: Yao Zi <[email protected]>
Reviewed-by: Leo Yu-Chi Liang <[email protected]>
| -rw-r--r-- | arch/riscv/cpu/th1520/cache.c | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/arch/riscv/cpu/th1520/cache.c b/arch/riscv/cpu/th1520/cache.c index 08aa1f789fd..b2fec229363 100644 --- a/arch/riscv/cpu/th1520/cache.c +++ b/arch/riscv/cpu/th1520/cache.c @@ -11,6 +11,7 @@ #define CSR_MHCR_IE BIT(0) #define CSR_MHCR_DE BIT(1) +#if CONFIG_IS_ENABLED(RISCV_MMODE) void icache_enable(void) { csr_write(CSR_MHCR, csr_read(CSR_MHCR) | CSR_MHCR_IE); @@ -30,3 +31,4 @@ int dcache_status(void) { return (csr_read(CSR_MHCR) & CSR_MHCR_DE) != 0; } +#endif /* CONFIG_IS_ENABLED(RISCV_MMODE) */ |