diff options
| author | J. Neuschäfer <[email protected]> | 2026-01-20 16:20:38 +0100 |
|---|---|---|
| committer | Andre Przywara <[email protected]> | 2026-01-25 23:29:32 +0000 |
| commit | 8805aa120ca5341ca14d8f7f2311f7a85d57a5f9 (patch) | |
| tree | 4f56e067e2aaf15c440a4685cd3ae2987119e477 | |
| parent | 61c2f29bde1d11a35664525d37c5806e61ec4304 (diff) | |
board: sunxi: Add X96Q support
The X96Q is a set-top box with an H313 SoC, AXP305 PMIC, 1 or 2 GiB RAM,
8 or 16 GiB eMMC flash, 2x USB A, Micro-SD, HDMI, Ethernet, audio/video
output, and infrared input.
https://x96mini.com/products/x96q-tv-box-android-10-set-top-box
This commit adds a defconfig and some documentation. The devicetree is
already in dts/upstream.
The CONFIG_DRAM_SUNXI_* settings are chosen such that the register
values in the DRAM PHY's MMIO space are as close as possible to those
observed when booting with the preinstalled vendor U-Boot. The DRAM
clock frequency of 600 MHz was reported in the vendor U-Boot's output.
Signed-off-by: J. Neuschäfer <[email protected]>
Reviewed-by: Andre Przywara <[email protected]>
| -rw-r--r-- | board/sunxi/MAINTAINERS | 5 | ||||
| -rw-r--r-- | configs/x96q_defconfig | 27 |
2 files changed, 32 insertions, 0 deletions
diff --git a/board/sunxi/MAINTAINERS b/board/sunxi/MAINTAINERS index c52e8a34c85..775d0f7ae83 100644 --- a/board/sunxi/MAINTAINERS +++ b/board/sunxi/MAINTAINERS @@ -611,6 +611,11 @@ M: Andre Przywara <[email protected]> S: Maintained F: configs/x96_mate_defconfig +X96Q TV BOX +M: J. Neuschäfer <[email protected]> +S: Maintained +F: configs/x96q_defconfig + X96Q PRO+ TV BOX M: Andre Przywara <[email protected]> S: Maintained diff --git a/configs/x96q_defconfig b/configs/x96q_defconfig new file mode 100644 index 00000000000..59f01aae4eb --- /dev/null +++ b/configs/x96q_defconfig @@ -0,0 +1,27 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_DEFAULT_DEVICE_TREE="allwinner/sun50i-h313-x96q" +CONFIG_DRAM_CLK=600 +CONFIG_SPL=y +CONFIG_DRAM_SUNXI_DX_ODT=0x03030303 +CONFIG_DRAM_SUNXI_DX_DRI=0x0e0e0e0e +CONFIG_DRAM_SUNXI_CA_DRI=0x1f12 +CONFIG_DRAM_SUNXI_TPR0=0xc0001002 +CONFIG_DRAM_SUNXI_TPR2=0x00000100 +CONFIG_DRAM_SUNXI_TPR10=0x002f0107 +CONFIG_DRAM_SUNXI_TPR11=0xddddcccc +CONFIG_DRAM_SUNXI_TPR12=0xeddc7665 +CONFIG_MACH_SUN50I_H616=y +CONFIG_SUNXI_DRAM_H616_DDR3_1333=y +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +CONFIG_R_I2C_ENABLE=y +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SPL_I2C=y +CONFIG_SPL_SYS_I2C_LEGACY=y +CONFIG_SYS_I2C_MVTWSI=y +CONFIG_SYS_I2C_SPEED=400000 +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_SUN8I_EMAC=y +CONFIG_AXP305_POWER=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OHCI_HCD=y |