Merge tag 'mediatek-for-main-2026-07-22' of https://git.u-boot-project.org/u-boot/custodians/u-boot-mediatek

Fixes: * Fixed some wrong parents of VLP clocks on mt8189. * Added a missing perficfg_ao clock in mt8188. * Disabled watchdog by default on Genio 510/700. * Fixed U-Boot DT overrides not included on Genio 510/700. Cleanups/refactoring: * Changed how clock parent providers are registered and looked up for all MediaTek targets. * Removed duplicate devicetree node in mt7623. * Removed unused/non-standard DT properties in mt798{1,6,8}. * Simplified MAINTAINERS by using N: instead of F: when possible. * Replaced duplicate driver names in all MediaTek clock drivers. * Cleaned up MediaTek power domain driver and split into separate driver per compatible target. * Removed unused power domain enablement from mt798{1,6,6a,7,8}. Features: * Added power domain driver for mt8188.
author: Tom Rini <[email protected]> 2026-07-23 10:55:18 -0600
committer: Tom Rini <[email protected]> 2026-07-23 10:55:18 -0600
commit: 88226db737b258c36141b66dabe5542b2407f5cd (patch)
tree: c5b58e3f7dba5fca5c71c8cb1996bcba0b1057c9
parent: a814edb52d93b6355c9ea1cb86ce29adb32ebbc2 (diff)
parent: d0c49353a648e135f269a2953dc9326505ba87de (diff)
51 files changed, 1745 insertions, 617 deletions
diff --git a/MAINTAINERS b/MAINTAINERS
index 323b1b172b1..53034b703df 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -418,46 +418,12 @@ R:	GSS_MTK_Uboot_upstream <[email protected]>
 T:	git https://git.u-boot-project.org/u-boot/custodians/u-boot-mediatek.git
 S:	Maintained
 F:	arch/arm/dts/mt*
-F:	arch/arm/mach-mediatek/
-F:	arch/arm/include/asm/arch-mediatek/
-F:	board/mediatek/
-F:	doc/device-tree-bindings/phy/phy-mtk-*
-F:	doc/device-tree-bindings/usb/mediatek,*
-F:	doc/README.mediatek
-F:	drivers/clk/mediatek/
-F:	drivers/cpu/mtk_cpu.c
-F:	drivers/i2c/mtk_i2c.c
-F:	drivers/mmc/mtk-sd.c
-F:	drivers/net/dwc_eth_qos_mtk.c
-F:	drivers/net/mtk_eth/
-F:	drivers/net/phy/mediatek/
-F:	drivers/phy/phy-mtk-*
-F:	drivers/pinctrl/mediatek/
-F:	drivers/power/domain/mtk-power-domain.c
-F:	drivers/power/pmic/mtk-pwrap.c
+F:	drivers/power/domain/mt*
 F:	drivers/power/regulator/mt*.c
-F:	drivers/pci/pcie_mediatek_gen3.c
-F:	drivers/pci/pcie_mediatek.c
-F:	drivers/pwm/pwm-mtk.c
-F:	drivers/ram/mediatek/
-F:	drivers/spi/mtk_snfi_spi.c
-F:	drivers/spi/mtk_spim.c
-F:	drivers/spi/mtk_snor.c
-F:	drivers/timer/mtk_timer.c
-F:	drivers/ufs/ufs-mediatek*
-F:	drivers/usb/host/xhci-mtk.c
 F:	drivers/usb/mtu3/
-F:	drivers/watchdog/mtk_wdt.c
-F:	drivers/reset/reset-mediatek.c
-F:	drivers/serial/serial_mtk.c
-F:	include/dt-bindings/clock/mediatek,*
-F:	include/dt-bindings/power/mediatek,*
 F:	include/power/mt*.h
-F:	tools/mtk_image.c
-F:	tools/mtk_image.h
-F:	tools/mtk_nand_headers.c
-F:	tools/mtk_nand_headers.h
 N:	mediatek
+N:	mtk
 
 ARM METHODE SUPPORT
 M:	Robert Marko <[email protected]>
diff --git a/arch/arm/dts/mt7623-u-boot.dtsi b/arch/arm/dts/mt7623-u-boot.dtsi
index b9fd49900ce..06414180f29 100644
--- a/arch/arm/dts/mt7623-u-boot.dtsi
+++ b/arch/arm/dts/mt7623-u-boot.dtsi
@@ -8,10 +8,6 @@
 	bootph-all;
 };
 
-&topckgen {
-	bootph-all;
-};
-
 &pericfg {
 	bootph-all;
 };
diff --git a/arch/arm/dts/mt7981.dtsi b/arch/arm/dts/mt7981.dtsi
index 5b4cadc22f7..675b14a0b7e 100644
--- a/arch/arm/dts/mt7981.dtsi
+++ b/arch/arm/dts/mt7981.dtsi
@@ -94,7 +94,6 @@
 	topckgen: topckgen@1001b000 {
 		compatible = "mediatek,mt7981-topckgen";
 		reg = <0x1001b000 0x1000>;
-		clock-parent = <&fixed_plls>;
 		#clock-cells = <1>;
 		bootph-all;
 	};
@@ -102,7 +101,6 @@
 	infracfg: infracfg@10001000 {
 		compatible = "mediatek,mt7981-infracfg";
 		reg = <0x10001000 0x30>;
-		clock-parent = <&topckgen>;
 		#clock-cells = <1>;
 		bootph-all;
 	};
@@ -221,7 +219,6 @@
 	ethsys: syscon@15000000 {
 		compatible = "mediatek,mt7981-ethsys", "syscon";
 		reg = <0x15000000 0x1000>;
-		clock-parent = <&topckgen>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
diff --git a/arch/arm/dts/mt7986.dtsi b/arch/arm/dts/mt7986.dtsi
index b2c57098a5e..5b62d8917ac 100644
--- a/arch/arm/dts/mt7986.dtsi
+++ b/arch/arm/dts/mt7986.dtsi
@@ -111,14 +111,12 @@
 	topckgen: topckgen@1001B000 {
 		compatible = "mediatek,mt7986-topckgen";
 		reg = <0x1001B000 0x1000>;
-		clock-parent = <&fixed_plls>;
 		#clock-cells = <1>;
 	};
 
 	infracfg: infracfg@10001040 {
 		compatible = "mediatek,mt7986-infracfg";
 		reg = <0x10001000 0x1000>;
-		clock-parent = <&topckgen>;
 		#clock-cells = <1>;
 	};
 
@@ -217,7 +215,6 @@
 	ethsys: syscon@15000000 {
 		compatible = "mediatek,mt7986-ethsys", "syscon";
 		reg = <0x15000000 0x1000>;
-		clock-parent = <&topckgen>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
diff --git a/arch/arm/dts/mt7988.dtsi b/arch/arm/dts/mt7988.dtsi
index 2d57c6f5709..0f7a85230d4 100644
--- a/arch/arm/dts/mt7988.dtsi
+++ b/arch/arm/dts/mt7988.dtsi
@@ -106,7 +106,6 @@
 	topckgen: topckgen@1001b000 {
 		compatible = "mediatek,mt7988-topckgen", "syscon";
 		reg = <0 0x1001b000 0 0x1000>;
-		clock-parent = <&apmixedsys>;
 		#clock-cells = <1>;
 	};
 
@@ -129,28 +128,24 @@
 	sgmiisys0: syscon@10060000 {
 		compatible = "mediatek,mt7988-sgmiisys_0", "syscon";
 		reg = <0 0x10060000 0 0x1000>;
-		clock-parent = <&topckgen>;
 		#clock-cells = <1>;
 	};
 
 	sgmiisys1: syscon@10070000 {
 		compatible = "mediatek,mt7988-sgmiisys_1", "syscon";
 		reg = <0 0x10070000 0 0x1000>;
-		clock-parent = <&topckgen>;
 		#clock-cells = <1>;
 	};
 
 	usxgmiisys0: syscon@10080000 {
 		compatible = "mediatek,mt7988-usxgmiisys_0", "syscon";
 		reg = <0 0x10080000 0 0x1000>;
-		clock-parent = <&topckgen>;
 		#clock-cells = <1>;
 	};
 
 	usxgmiisys1: syscon@10081000 {
 		compatible = "mediatek,mt7988-usxgmiisys_1", "syscon";
 		reg = <0 0x10081000 0 0x1000>;
-		clock-parent = <&topckgen>;
 		#clock-cells = <1>;
 	};
 
@@ -378,21 +373,18 @@
 	xfi_pextp0: syscon@11f20000 {
 		compatible = "mediatek,mt7988-xfi_pextp_0", "syscon";
 		reg = <0 0x11f20000 0 0x10000>;
-		clock-parent = <&topckgen>;
 		#clock-cells = <1>;
 	};
 
 	xfi_pextp1: syscon@11f30000 {
 		compatible = "mediatek,mt7988-xfi_pextp_1", "syscon";
 		reg = <0 0x11f30000 0 0x10000>;
-		clock-parent = <&topckgen>;
 		#clock-cells = <1>;
 	};
 
 	xfi_pll: syscon@11f40000 {
 		compatible = "mediatek,mt7988-xfi_pll", "syscon";
 		reg = <0 0x11f40000 0 0x1000>;
-		clock-parent = <&topckgen>;
 		#clock-cells = <1>;
 	};
 
@@ -400,14 +392,12 @@
 		compatible = "mediatek,mt7988-topmisc", "syscon",
 			     "mediatek,mt7988-power-controller";
 		reg = <0 0x11d10000 0 0x10000>;
-		clock-parent = <&topckgen>;
 		#clock-cells = <1>;
 	};
 
 	infracfg: infracfg@10001000 {
 		compatible = "mediatek,mt7988-infracfg", "syscon";
 		reg = <0 0x10001000 0 0x1000>;
-		clock-parent = <&topckgen>;
 		#clock-cells = <1>;
 	};
 
@@ -572,7 +562,6 @@
 	ethdma: syscon@15000000 {
 		compatible = "mediatek,mt7988-ethdma", "syscon";
 		reg = <0 0x15000000 0 0x20000>;
-		clock-parent = <&topckgen>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
@@ -580,7 +569,6 @@
 	ethwarp: syscon@15031000 {
 		compatible = "mediatek,mt7988-ethwarp", "syscon";
 		reg = <0 0x15031000 0 0x1000>;
-		clock-parent = <&topckgen>;
 		#clock-cells = <1>;
 		#reset-cells = <1>;
 	};
diff --git a/arch/arm/dts/mt8370-genio-510-evk-u-boot.dtsi b/arch/arm/dts/mt8370-genio-510-evk-u-boot.dtsi
new file mode 100644
index 00000000000..586d15bf72e
--- /dev/null
+++ b/arch/arm/dts/mt8370-genio-510-evk-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2026 BayLibre, SAS.
+ * Author: Julien Stephan <[email protected]>
+ */
+
+#include "mt8188-u-boot.dtsi"
diff --git a/arch/arm/dts/mt8390-genio-700-evk-u-boot.dtsi b/arch/arm/dts/mt8390-genio-700-evk-u-boot.dtsi
new file mode 100644
index 00000000000..586d15bf72e
--- /dev/null
+++ b/arch/arm/dts/mt8390-genio-700-evk-u-boot.dtsi
@@ -0,0 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2026 BayLibre, SAS.
+ * Author: Julien Stephan <[email protected]>
+ */
+
+#include "mt8188-u-boot.dtsi"
diff --git a/arch/arm/mach-mediatek/mt7629/init.c b/arch/arm/mach-mediatek/mt7629/init.c
index ff027ed03ef..d12eb5339e9 100644
--- a/arch/arm/mach-mediatek/mt7629/init.c
+++ b/arch/arm/mach-mediatek/mt7629/init.c
@@ -41,7 +41,7 @@ static int mtk_pll_early_init(void)
 	int ret, i;
 
 	ret = uclass_get_device_by_driver(UCLASS_CLK,
-			DM_DRIVER_GET(mtk_clk_apmixedsys), &dev);
+			DM_DRIVER_GET(mt7629_clk_apmixedsys), &dev);
 	if (ret)
 		return ret;
 
@@ -60,7 +60,7 @@ static int mtk_pll_early_init(void)
 
 	/* setup mcu bus */
 	ret = uclass_get_device_by_driver(UCLASS_SYSCON,
-			DM_DRIVER_GET(mtk_mcucfg), &dev);
+			DM_DRIVER_GET(mt7629_mcucfg), &dev);
 	if (ret)
 		return ret;
 
diff --git a/arch/arm/mach-mediatek/mt8516/init.c b/arch/arm/mach-mediatek/mt8516/init.c
index b470910da7f..d9fe8fc8505 100644
--- a/arch/arm/mach-mediatek/mt8516/init.c
+++ b/arch/arm/mach-mediatek/mt8516/init.c
@@ -44,7 +44,7 @@ static int mtk_pll_early_init(void)
 	int ret, i;
 
 	ret = uclass_get_device_by_driver(UCLASS_CLK,
-			DM_DRIVER_GET(mtk_clk_apmixedsys), &dev);
+			DM_DRIVER_GET(mt8516_clk_apmixedsys), &dev);
 	if (ret)
 		return ret;
 
diff --git a/board/mediatek/MAINTAINERS b/board/mediatek/MAINTAINERS
index 37ca35b4dd4..d99c6d708b2 100644
--- a/board/mediatek/MAINTAINERS
+++ b/board/mediatek/MAINTAINERS
@@ -21,6 +21,9 @@ MT8188/MT8370/MT8390
 M:	Macpaul Lin <[email protected]>
 M:	Julien Stephan <[email protected]>
 S:	Maintained
+F:	arch/arm/dts/mt8188-u-boot.dtsi
+F:	arch/arm/dts/mt8370-genio-510-evk-u-boot.dtsi
+F:	arch/arm/dts/mt8390-genio-700-evk-u-boot.dtsi
 F:	configs/mt8188.config
 F:	configs/mt8370_genio_510_evk_defconfig
 F:	configs/mt8390_genio_700_evk_defconfig
diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig
index b3b688ff825..10df7847a4b 100644
--- a/configs/mt7622_rfb_defconfig
+++ b/configs/mt7622_rfb_defconfig
@@ -51,7 +51,7 @@ CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_PINCTRL_MT7622=y
 CONFIG_POWER_DOMAIN=y
-CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_MT7622_POWER_DOMAIN=y
 CONFIG_RAM=y
 CONFIG_DM_SERIAL=y
 CONFIG_MTK_SERIAL=y
diff --git a/configs/mt7623a_unielec_u7623_02_defconfig b/configs/mt7623a_unielec_u7623_02_defconfig
index 826f49a9626..77473e2731f 100644
--- a/configs/mt7623a_unielec_u7623_02_defconfig
+++ b/configs/mt7623a_unielec_u7623_02_defconfig
@@ -49,7 +49,7 @@ CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_PINCTRL_MT7623=y
 CONFIG_POWER_DOMAIN=y
-CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_MT2701_POWER_DOMAIN=y
 CONFIG_DM_SERIAL=y
 CONFIG_MTK_SERIAL=y
 CONFIG_SYSRESET=y
diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig
index aeef3bebe96..aacaf5380fa 100644
--- a/configs/mt7623n_bpir2_defconfig
+++ b/configs/mt7623n_bpir2_defconfig
@@ -51,7 +51,7 @@ CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_PINCTRL_MT7623=y
 CONFIG_POWER_DOMAIN=y
-CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_MT2701_POWER_DOMAIN=y
 CONFIG_DM_SERIAL=y
 CONFIG_MTK_SERIAL=y
 CONFIG_SYSRESET=y
diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig
index 72b1c83312e..91da684939a 100644
--- a/configs/mt7629_rfb_defconfig
+++ b/configs/mt7629_rfb_defconfig
@@ -83,7 +83,7 @@ CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_PINCTRL_MT7629=y
 CONFIG_POWER_DOMAIN=y
-CONFIG_MTK_POWER_DOMAIN=y
+CONFIG_MT7622_POWER_DOMAIN=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_RAM=y
diff --git a/configs/mt7981_emmc_rfb_defconfig b/configs/mt7981_emmc_rfb_defconfig
index e5f193b7233..75e7140bdfa 100644
--- a/configs/mt7981_emmc_rfb_defconfig
+++ b/configs/mt7981_emmc_rfb_defconfig
@@ -52,8 +52,6 @@ CONFIG_PHY_FIXED=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_PINCTRL_MT7981=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_MTK_POWER_DOMAIN=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/mt7981_rfb_defconfig b/configs/mt7981_rfb_defconfig
index bf361bc3ccc..6322af51b18 100644
--- a/configs/mt7981_rfb_defconfig
+++ b/configs/mt7981_rfb_defconfig
@@ -54,8 +54,6 @@ CONFIG_PHY_FIXED=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_PINCTRL_MT7981=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_MTK_POWER_DOMAIN=y
 CONFIG_DM_SERIAL=y
 CONFIG_MTK_SERIAL=y
 CONFIG_SPI=y
diff --git a/configs/mt7981_sd_rfb_defconfig b/configs/mt7981_sd_rfb_defconfig
index f77d80f3a0a..de05e2486a0 100644
--- a/configs/mt7981_sd_rfb_defconfig
+++ b/configs/mt7981_sd_rfb_defconfig
@@ -52,8 +52,6 @@ CONFIG_PHY_FIXED=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_PINCTRL_MT7981=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_MTK_POWER_DOMAIN=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/mt7986_rfb_defconfig b/configs/mt7986_rfb_defconfig
index 2cbed019147..87fbe677624 100644
--- a/configs/mt7986_rfb_defconfig
+++ b/configs/mt7986_rfb_defconfig
@@ -54,8 +54,6 @@ CONFIG_PHY_FIXED=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_PINCTRL_MT7986=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_MTK_POWER_DOMAIN=y
 CONFIG_DM_SERIAL=y
 CONFIG_MTK_SERIAL=y
 CONFIG_SPI=y
diff --git a/configs/mt7986a_bpir3_emmc_defconfig b/configs/mt7986a_bpir3_emmc_defconfig
index 80962adb43a..92459ad9fe2 100644
--- a/configs/mt7986a_bpir3_emmc_defconfig
+++ b/configs/mt7986a_bpir3_emmc_defconfig
@@ -52,8 +52,6 @@ CONFIG_PHY_FIXED=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_PINCTRL_MT7986=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_MTK_POWER_DOMAIN=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/mt7986a_bpir3_sd_defconfig b/configs/mt7986a_bpir3_sd_defconfig
index 0b91b275500..2c88255e69d 100644
--- a/configs/mt7986a_bpir3_sd_defconfig
+++ b/configs/mt7986a_bpir3_sd_defconfig
@@ -52,8 +52,6 @@ CONFIG_PHY_FIXED=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_PINCTRL_MT7986=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_MTK_POWER_DOMAIN=y
 CONFIG_DM_REGULATOR=y
 CONFIG_DM_REGULATOR_FIXED=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/mt7987_emmc_rfb_defconfig b/configs/mt7987_emmc_rfb_defconfig
index 11673f9a1f2..00d7e5a610a 100644
--- a/configs/mt7987_emmc_rfb_defconfig
+++ b/configs/mt7987_emmc_rfb_defconfig
@@ -77,8 +77,6 @@ CONFIG_PHY_ETHERNET_ID=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_PINCTRL_MT7987=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_MTK_POWER_DOMAIN=y
 CONFIG_DM_PWM=y
 CONFIG_PWM_MTK=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/mt7987_rfb_defconfig b/configs/mt7987_rfb_defconfig
index fd2c67de4f8..0b353c6cf01 100644
--- a/configs/mt7987_rfb_defconfig
+++ b/configs/mt7987_rfb_defconfig
@@ -72,8 +72,6 @@ CONFIG_PHY_ETHERNET_ID=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_PINCTRL_MT7987=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_MTK_POWER_DOMAIN=y
 CONFIG_DM_PWM=y
 CONFIG_PWM_MTK=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/mt7987_sd_rfb_defconfig b/configs/mt7987_sd_rfb_defconfig
index b8e01475b22..30ff09365da 100644
--- a/configs/mt7987_sd_rfb_defconfig
+++ b/configs/mt7987_sd_rfb_defconfig
@@ -77,8 +77,6 @@ CONFIG_PHY_ETHERNET_ID=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_PINCTRL_MT7987=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_MTK_POWER_DOMAIN=y
 CONFIG_DM_PWM=y
 CONFIG_PWM_MTK=y
 CONFIG_DM_SERIAL=y
diff --git a/configs/mt7988_rfb_defconfig b/configs/mt7988_rfb_defconfig
index 8230628312d..375df418ce0 100644
--- a/configs/mt7988_rfb_defconfig
+++ b/configs/mt7988_rfb_defconfig
@@ -67,8 +67,6 @@ CONFIG_PHY_FIXED=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_PINCTRL_MT7988=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_MTK_POWER_DOMAIN=y
 CONFIG_DM_PWM=y
 CONFIG_PWM_MTK=y
 CONFIG_RAM=y
diff --git a/configs/mt7988_sd_rfb_defconfig b/configs/mt7988_sd_rfb_defconfig
index db3ca7801f9..aafbed7bea5 100644
--- a/configs/mt7988_sd_rfb_defconfig
+++ b/configs/mt7988_sd_rfb_defconfig
@@ -55,8 +55,6 @@ CONFIG_PHY_FIXED=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_PINCTRL_MT7988=y
-CONFIG_POWER_DOMAIN=y
-CONFIG_MTK_POWER_DOMAIN=y
 CONFIG_DM_PWM=y
 CONFIG_PWM_MTK=y
 CONFIG_RAM=y
diff --git a/configs/mt8188.config b/configs/mt8188.config
index 0f748415602..29e2b3db878 100644
--- a/configs/mt8188.config
+++ b/configs/mt8188.config
@@ -19,9 +19,12 @@ CONFIG_MMC_MTK=y
 CONFIG_PINCTRL=y
 CONFIG_PINCONF=y
 CONFIG_PINCTRL_MT8188=y
+CONFIG_POWER_DOMAIN=y
+CONFIG_MT8188_POWER_DOMAIN=y
 CONFIG_BAUDRATE=921600
 CONFIG_DM_SERIAL=y
 CONFIG_MTK_SERIAL=y
+# CONFIG_WATCHDOG_AUTOSTART is not set
 CONFIG_WDT=y
 CONFIG_WDT_MTK=y
 # CONFIG_RANDOM_UUID is not set
diff --git a/configs/mt8365_evk_defconfig b/configs/mt8365_evk_defconfig
index 202879ba66d..5db8418e36f 100644
--- a/configs/mt8365_evk_defconfig
+++ b/configs/mt8365_evk_defconfig
@@ -31,5 +31,6 @@ CONFIG_DM_REGULATOR_MT6357=y
 CONFIG_BAUDRATE=921600
 CONFIG_DM_SERIAL=y
 CONFIG_MTK_SERIAL=y
+# CONFIG_WATCHDOG_AUTOSTART is not set
 CONFIG_WDT=y
 CONFIG_WDT_MTK=y
diff --git a/drivers/clk/mediatek/clk-mt7622.c b/drivers/clk/mediatek/clk-mt7622.c
index 79315912fd4..76bc31f06d2 100644
--- a/drivers/clk/mediatek/clk-mt7622.c
+++ b/drivers/clk/mediatek/clk-mt7622.c
@@ -85,7 +85,7 @@ static const struct mtk_gate_regs apmixed_cg_regs = {
 		.parent = _parent,			\
 		.regs = &apmixed_cg_regs,		\
 		.shift = _shift,			\
-		.flags = CLK_GATE_NO_SETCLR_INV,	\
+		.flags = CLK_GATE_NO_SETCLR_INV | CLK_PARENT_APMIXED,	\
 	}
 
 static const struct mtk_gate apmixed_cgs[] = {
@@ -613,6 +613,21 @@ static const struct mtk_clk_tree mt7622_apmixed_clk_tree = {
 	.gates = apmixed_cgs,
 	.num_plls = ARRAY_SIZE(apmixed_plls),
 	.num_gates = ARRAY_SIZE(apmixed_cgs),
+	.type = MTK_CLK_TREE_APMIXED,
+};
+
+static const struct mtk_clk_tree mt7622_topckgen_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.fdivs_offs = CLK_TOP_TO_USB3_SYS,
+	.muxes_offs = CLK_TOP_AXI_SEL,
+	.fclks = top_fixed_clks,
+	.fdivs = top_fixed_divs,
+	.muxes = top_muxes,
+	.num_fclks = ARRAY_SIZE(top_fixed_clks),
+	.num_fdivs = ARRAY_SIZE(top_fixed_divs),
+	.num_muxes = ARRAY_SIZE(top_muxes),
+	.type = MTK_CLK_TREE_TOPCKGEN,
 };
 
 static const struct mtk_clk_tree mt7622_infra_clk_tree = {
@@ -640,14 +655,6 @@ static const struct mtk_clk_tree mt7622_peri_clk_tree = {
 static const struct mtk_clk_tree mt7622_clk_tree = {
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
-	.fdivs_offs = CLK_TOP_TO_USB3_SYS,
-	.muxes_offs = CLK_TOP_AXI_SEL,
-	.fclks = top_fixed_clks,
-	.fdivs = top_fixed_divs,
-	.muxes = top_muxes,
-	.num_fclks = ARRAY_SIZE(top_fixed_clks),
-	.num_fdivs = ARRAY_SIZE(top_fixed_divs),
-	.num_muxes = ARRAY_SIZE(top_muxes),
 };
 
 static int mt7622_mcucfg_probe(struct udevice *dev)
@@ -687,17 +694,17 @@ static int mt7622_apmixedsys_probe(struct udevice *dev)
 
 static int mt7622_topckgen_probe(struct udevice *dev)
 {
-	return mtk_common_clk_init(dev, &mt7622_clk_tree);
+	return mtk_common_clk_init(dev, &mt7622_topckgen_clk_tree);
 }
 
 static int mt7622_infracfg_probe(struct udevice *dev)
 {
-	return mtk_common_clk_infrasys_init(dev, &mt7622_infra_clk_tree);
+	return mtk_common_clk_init(dev, &mt7622_infra_clk_tree);
 }
 
 static int mt7622_pericfg_probe(struct udevice *dev)
 {
-	return mtk_common_clk_infrasys_init(dev, &mt7622_peri_clk_tree);
+	return mtk_common_clk_init(dev, &mt7622_peri_clk_tree);
 }
 
 static int mt7622_pciesys_probe(struct udevice *dev)
@@ -795,7 +802,7 @@ static const struct udevice_id mt7622_ssusbsys_compat[] = {
 	{ }
 };
 
-U_BOOT_DRIVER(mtk_mcucfg) = {
+U_BOOT_DRIVER(mt7622_mcucfg) = {
 	.name = "mt7622-mcucfg",
 	.id = UCLASS_SYSCON,
 	.of_match = mt7622_mcucfg_compat,
@@ -803,27 +810,29 @@ U_BOOT_DRIVER(mtk_mcucfg) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+U_BOOT_DRIVER(mt7622_clk_apmixedsys) = {
 	.name = "mt7622-clock-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7622_apmixed_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7622_apmixedsys_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_topckgen) = {
+U_BOOT_DRIVER(mt7622_clk_topckgen) = {
 	.name = "mt7622-clock-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt7622_topckgen_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7622_topckgen_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_infracfg) = {
+U_BOOT_DRIVER(mt7622_clk_infracfg) = {
 	.name = "mt7622-clock-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7622_infracfg_compat,
@@ -833,7 +842,7 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_pericfg) = {
+U_BOOT_DRIVER(mt7622_clk_pericfg) = {
 	.name = "mt7622-clock-pericfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7622_pericfg_compat,
@@ -843,7 +852,7 @@ U_BOOT_DRIVER(mtk_clk_pericfg) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_pciesys) = {
+U_BOOT_DRIVER(mt7622_clk_pciesys) = {
 	.name = "mt7622-clock-pciesys",
 	.id = UCLASS_CLK,
 	.of_match = mt7622_pciesys_compat,
@@ -853,7 +862,7 @@ U_BOOT_DRIVER(mtk_clk_pciesys) = {
 	.ops = &mtk_clk_gate_ops,
 };
 
-U_BOOT_DRIVER(mtk_clk_ethsys) = {
+U_BOOT_DRIVER(mt7622_clk_ethsys) = {
 	.name = "mt7622-clock-ethsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7622_ethsys_compat,
@@ -863,7 +872,7 @@ U_BOOT_DRIVER(mtk_clk_ethsys) = {
 	.ops = &mtk_clk_gate_ops,
 };
 
-U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
+U_BOOT_DRIVER(mt7622_clk_sgmiisys) = {
 	.name = "mt7622-clock-sgmiisys",
 	.id = UCLASS_CLK,
 	.of_match = mt7622_sgmiisys_compat,
@@ -872,7 +881,7 @@ U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
 	.ops = &mtk_clk_gate_ops,
 };
 
-U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
+U_BOOT_DRIVER(mt7622_clk_ssusbsys) = {
 	.name = "mt7622-clock-ssusbsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7622_ssusbsys_compat,
diff --git a/drivers/clk/mediatek/clk-mt7623.c b/drivers/clk/mediatek/clk-mt7623.c
index 0a302b405e2..56912ebdb53 100644
--- a/drivers/clk/mediatek/clk-mt7623.c
+++ b/drivers/clk/mediatek/clk-mt7623.c
@@ -1009,6 +1009,7 @@ static const struct mtk_clk_tree mt7623_apmixedsys_clk_tree = {
 	.id_offs_map_size = ARRAY_SIZE(pll_id_offs_map),
 	.plls = apmixed_plls,
 	.num_plls = ARRAY_SIZE(apmixed_plls),
+	.type = MTK_CLK_TREE_APMIXED,
 };
 
 static const struct mtk_clk_tree mt7623_topckgen_clk_tree = {
@@ -1024,6 +1025,7 @@ static const struct mtk_clk_tree mt7623_topckgen_clk_tree = {
 	.num_fclks = ARRAY_SIZE(top_fixed_clks),
 	.num_fdivs = ARRAY_SIZE(top_fixed_divs),
 	.num_muxes = ARRAY_SIZE(top_muxes),
+	.type = MTK_CLK_TREE_TOPCKGEN,
 };
 
 static int mt7623_mcucfg_probe(struct udevice *dev)
@@ -1088,7 +1090,7 @@ static const struct mtk_clk_tree mt7623_clk_peri_tree = {
 
 static int mt7623_pericfg_probe(struct udevice *dev)
 {
-	return mtk_common_clk_infrasys_init(dev, &mt7623_clk_peri_tree);
+	return mtk_common_clk_init(dev, &mt7623_clk_peri_tree);
 }
 
 static int mt7623_hifsys_probe(struct udevice *dev)
@@ -1151,7 +1153,7 @@ static const struct udevice_id mt7623_mcucfg_compat[] = {
 	{ }
 };
 
-U_BOOT_DRIVER(mtk_mcucfg) = {
+U_BOOT_DRIVER(mt7623_mcucfg) = {
 	.name = "mt7623-mcucfg",
 	.id = UCLASS_SYSCON,
 	.of_match = mt7623_mcucfg_compat,
@@ -1159,27 +1161,29 @@ U_BOOT_DRIVER(mtk_mcucfg) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+U_BOOT_DRIVER(mt7623_clk_apmixedsys) = {
 	.name = "mt7623-clock-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7623_apmixed_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7623_apmixedsys_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_topckgen) = {
+U_BOOT_DRIVER(mt7623_clk_topckgen) = {
 	.name = "mt7623-clock-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt7623_topckgen_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7623_topckgen_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_infracfg) = {
+U_BOOT_DRIVER(mt7623_clk_infracfg) = {
 	.name = "mt7623-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7623_infracfg_compat,
@@ -1189,7 +1193,7 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_pericfg) = {
+U_BOOT_DRIVER(mt7623_clk_pericfg) = {
 	.name = "mt7623-pericfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7623_pericfg_compat,
@@ -1199,7 +1203,7 @@ U_BOOT_DRIVER(mtk_clk_pericfg) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_hifsys) = {
+U_BOOT_DRIVER(mt7623_clk_hifsys) = {
 	.name = "mt7623-clock-hifsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7623_hifsys_compat,
@@ -1209,7 +1213,7 @@ U_BOOT_DRIVER(mtk_clk_hifsys) = {
 	.ops = &mtk_clk_gate_ops,
 };
 
-U_BOOT_DRIVER(mtk_clk_ethsys) = {
+U_BOOT_DRIVER(mt7623_clk_ethsys) = {
 	.name = "mt7623-clock-ethsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7623_ethsys_compat,
diff --git a/drivers/clk/mediatek/clk-mt7629.c b/drivers/clk/mediatek/clk-mt7629.c
index 74510ee36a9..aee340aeb37 100644
--- a/drivers/clk/mediatek/clk-mt7629.c
+++ b/drivers/clk/mediatek/clk-mt7629.c
@@ -575,36 +575,32 @@ static const struct mtk_gate ssusb_cgs[] = {
 	GATE_SSUSB(CLK_SSUSB_DMA_EN, CLK_TOP_TO_USB3_DMA, 8),
 };
 
-static const struct mtk_clk_tree mt7629_clk_tree = {
+static const struct mtk_clk_tree mt7629_apmixed_clk_tree = {
 	.pll_parent = EXT_PARENT(CLK_PAD_CLK20M),
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
-	.fdivs_offs = CLK_TOP_TO_USB3_SYS,
-	.muxes_offs = CLK_TOP_AXI_SEL,
 	.plls = apmixed_plls,
-	.fclks = top_fixed_clks,
-	.fdivs = top_fixed_divs,
-	.muxes = top_muxes,
 	.num_plls = ARRAY_SIZE(apmixed_plls),
-	.num_fclks = ARRAY_SIZE(top_fixed_clks),
-	.num_fdivs = ARRAY_SIZE(top_fixed_divs),
-	.num_muxes = ARRAY_SIZE(top_muxes),
+	.type = MTK_CLK_TREE_APMIXED,
 };
 
-static const struct mtk_clk_tree mt7629_peri_clk_tree = {
-	.pll_parent = EXT_PARENT(CLK_PAD_CLK20M),
+static const struct mtk_clk_tree mt7629_topckgen_clk_tree = {
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
 	.fdivs_offs = CLK_TOP_TO_USB3_SYS,
 	.muxes_offs = CLK_TOP_AXI_SEL,
-	.plls = apmixed_plls,
 	.fclks = top_fixed_clks,
 	.fdivs = top_fixed_divs,
 	.muxes = top_muxes,
-	.num_plls = ARRAY_SIZE(apmixed_plls),
 	.num_fclks = ARRAY_SIZE(top_fixed_clks),
 	.num_fdivs = ARRAY_SIZE(top_fixed_divs),
 	.num_muxes = ARRAY_SIZE(top_muxes),
+	.type = MTK_CLK_TREE_TOPCKGEN,
+};
+
+static const struct mtk_clk_tree mt7629_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
 };
 
 static int mt7629_mcucfg_probe(struct udevice *dev)
@@ -628,7 +624,7 @@ static int mt7629_apmixedsys_probe(struct udevice *dev)
 	struct mtk_clk_priv *priv = dev_get_priv(dev);
 	int ret;
 
-	ret = mtk_common_clk_init(dev, &mt7629_clk_tree);
+	ret = mtk_common_clk_init(dev, &mt7629_apmixed_clk_tree);
 	if (ret)
 		return ret;
 
@@ -642,7 +638,7 @@ static int mt7629_apmixedsys_probe(struct udevice *dev)
 
 static int mt7629_topckgen_probe(struct udevice *dev)
 {
-	return mtk_common_clk_init(dev, &mt7629_clk_tree);
+	return mtk_common_clk_init(dev, &mt7629_topckgen_clk_tree);
 }
 
 static int mt7629_infracfg_probe(struct udevice *dev)
@@ -653,7 +649,7 @@ static int mt7629_infracfg_probe(struct udevice *dev)
 
 static int mt7629_pericfg_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7629_peri_clk_tree, peri_cgs,
+	return mtk_common_clk_gate_init(dev, &mt7629_clk_tree, peri_cgs,
 					ARRAY_SIZE(peri_cgs), CLK_PERI_PWM1_PD);
 }
 
@@ -728,7 +724,7 @@ static const struct udevice_id mt7629_mcucfg_compat[] = {
 	{ }
 };
 
-U_BOOT_DRIVER(mtk_mcucfg) = {
+U_BOOT_DRIVER(mt7629_mcucfg) = {
 	.name = "mt7629-mcucfg",
 	.id = UCLASS_SYSCON,
 	.of_match = mt7629_mcucfg_compat,
@@ -736,27 +732,29 @@ U_BOOT_DRIVER(mtk_mcucfg) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+U_BOOT_DRIVER(mt7629_clk_apmixedsys) = {
 	.name = "mt7629-clock-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7629_apmixed_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7629_apmixedsys_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_topckgen) = {
+U_BOOT_DRIVER(mt7629_clk_topckgen) = {
 	.name = "mt7629-clock-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt7629_topckgen_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7629_topckgen_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_infracfg) = {
+U_BOOT_DRIVER(mt7629_clk_infracfg) = {
 	.name = "mt7629-clock-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7629_infracfg_compat,
@@ -766,7 +764,7 @@ U_BOOT_DRIVER(mtk_clk_infracfg) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_pericfg) = {
+U_BOOT_DRIVER(mt7629_clk_pericfg) = {
 	.name = "mt7629-clock-pericfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7629_pericfg_compat,
@@ -776,7 +774,7 @@ U_BOOT_DRIVER(mtk_clk_pericfg) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_ethsys) = {
+U_BOOT_DRIVER(mt7629_clk_ethsys) = {
 	.name = "mt7629-clock-ethsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7629_ethsys_compat,
@@ -786,7 +784,7 @@ U_BOOT_DRIVER(mtk_clk_ethsys) = {
 	.ops = &mtk_clk_gate_ops,
 };
 
-U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
+U_BOOT_DRIVER(mt7629_clk_sgmiisys) = {
 	.name = "mt7629-clock-sgmiisys",
 	.id = UCLASS_CLK,
 	.of_match = mt7629_sgmiisys_compat,
@@ -795,7 +793,7 @@ U_BOOT_DRIVER(mtk_clk_sgmiisys) = {
 	.ops = &mtk_clk_gate_ops,
 };
 
-U_BOOT_DRIVER(mtk_clk_ssusbsys) = {
+U_BOOT_DRIVER(mt7629_clk_ssusbsys) = {
 	.name = "mt7629-clock-ssusbsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7629_ssusbsys_compat,
diff --git a/drivers/clk/mediatek/clk-mt7981.c b/drivers/clk/mediatek/clk-mt7981.c
index 8c2944b7fb3..4e3a1c9d835 100644
--- a/drivers/clk/mediatek/clk-mt7981.c
+++ b/drivers/clk/mediatek/clk-mt7981.c
@@ -622,6 +622,7 @@ static const struct mtk_clk_tree mt7981_fixed_pll_clk_tree = {
 	.fdivs_offs = CLK_APMIXED_NR_CLK,
 	.fclks = fixed_pll_clks,
 	.num_fclks = ARRAY_SIZE(fixed_pll_clks),
+	.type = MTK_CLK_TREE_APMIXED,
 };
 
 static const struct mtk_clk_tree mt7981_topckgen_clk_tree = {
@@ -636,6 +637,7 @@ static const struct mtk_clk_tree mt7981_topckgen_clk_tree = {
 	.num_fdivs = ARRAY_SIZE(top_fixed_divs),
 	.num_muxes = ARRAY_SIZE(top_muxes),
 	.flags = CLK_PARENT_TOPCKGEN,
+	.type = MTK_CLK_TREE_TOPCKGEN,
 };
 
 static const struct mtk_clk_tree mt7981_infracfg_clk_tree = {
@@ -651,6 +653,12 @@ static const struct mtk_clk_tree mt7981_infracfg_clk_tree = {
 	.num_muxes = ARRAY_SIZE(infra_muxes),
 	.num_gates = ARRAY_SIZE(infracfg_gates),
 	.flags = CLK_PARENT_INFRASYS,
+	.type = MTK_CLK_TREE_INFRASYS,
+};
+
+static const struct mtk_clk_tree mt7981_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
 };
 
 static const struct udevice_id mt7981_fixed_pll_compat[] = {
@@ -679,20 +687,22 @@ static int mt7981_topckgen_probe(struct udevice *dev)
 	return mtk_common_clk_init(dev, &mt7981_topckgen_clk_tree);
 }
 
-U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+U_BOOT_DRIVER(mt7981_clk_apmixedsys) = {
 	.name = "mt7981-clock-fixed-pll",
 	.id = UCLASS_CLK,
 	.of_match = mt7981_fixed_pll_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7981_fixed_pll_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_fixed_pll_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_topckgen) = {
+U_BOOT_DRIVER(mt7981_clk_topckgen) = {
 	.name = "mt7981-clock-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt7981_topckgen_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7981_topckgen_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
@@ -706,13 +716,14 @@ static const struct udevice_id mt7981_infracfg_compat[] = {
 
 static int mt7981_infracfg_probe(struct udevice *dev)
 {
-	return mtk_common_clk_infrasys_init(dev, &mt7981_infracfg_clk_tree);
+	return mtk_common_clk_init(dev, &mt7981_infracfg_clk_tree);
 }
 
-U_BOOT_DRIVER(mtk_clk_infracfg) = {
+U_BOOT_DRIVER(mt7981_clk_infracfg) = {
 	.name = "mt7981-clock-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7981_infracfg_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7981_infracfg_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
@@ -742,7 +753,7 @@ static const struct mtk_gate sgmii0_cgs[] = {
 
 static int mt7981_sgmii0sys_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree,
+	return mtk_common_clk_gate_init(dev, &mt7981_clk_tree,
 					sgmii0_cgs, ARRAY_SIZE(sgmii0_cgs), 0);
 }
 
@@ -751,7 +762,7 @@ static const struct udevice_id mt7981_sgmii0sys_compat[] = {
 	{}
 };
 
-U_BOOT_DRIVER(mtk_clk_sgmii0sys) = {
+U_BOOT_DRIVER(mt7981_clk_sgmii0sys) = {
 	.name = "mt7981-clock-sgmii0sys",
 	.id = UCLASS_CLK,
 	.of_match = mt7981_sgmii0sys_compat,
@@ -769,7 +780,7 @@ static const struct mtk_gate sgmii1_cgs[] = {
 
 static int mt7981_sgmii1sys_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree,
+	return mtk_common_clk_gate_init(dev, &mt7981_clk_tree,
 					sgmii1_cgs, ARRAY_SIZE(sgmii1_cgs), 0);
 }
 
@@ -778,7 +789,7 @@ static const struct udevice_id mt7981_sgmii1sys_compat[] = {
 	{}
 };
 
-U_BOOT_DRIVER(mtk_clk_sgmii1sys) = {
+U_BOOT_DRIVER(mt7981_clk_sgmii1sys) = {
 	.name = "mt7981-clock-sgmii1sys",
 	.id = UCLASS_CLK,
 	.of_match = mt7981_sgmii1sys_compat,
@@ -810,7 +821,7 @@ static const struct mtk_gate eth_cgs[] = {
 
 static int mt7981_ethsys_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7981_topckgen_clk_tree,
+	return mtk_common_clk_gate_init(dev, &mt7981_clk_tree,
 					eth_cgs, ARRAY_SIZE(eth_cgs), 0);
 }
 
@@ -832,7 +843,7 @@ static const struct udevice_id mt7981_ethsys_compat[] = {
 	{}
 };
 
-U_BOOT_DRIVER(mtk_clk_ethsys) = {
+U_BOOT_DRIVER(mt7981_clk_ethsys) = {
 	.name = "mt7981-clock-ethsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7981_ethsys_compat,
diff --git a/drivers/clk/mediatek/clk-mt7986.c b/drivers/clk/mediatek/clk-mt7986.c
index 9c6514120a6..56e18d403c8 100644
--- a/drivers/clk/mediatek/clk-mt7986.c
+++ b/drivers/clk/mediatek/clk-mt7986.c
@@ -530,6 +530,7 @@ static const struct mtk_clk_tree mt7986_fixed_pll_clk_tree = {
 	.fclks = fixed_pll_clks,
 	.num_fclks = ARRAY_SIZE(fixed_pll_clks),
 	.flags = CLK_PARENT_APMIXED,
+	.type = MTK_CLK_TREE_APMIXED,
 };
 
 static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {
@@ -544,6 +545,7 @@ static const struct mtk_clk_tree mt7986_topckgen_clk_tree = {
 	.num_fdivs = ARRAY_SIZE(top_fixed_divs),
 	.num_muxes = ARRAY_SIZE(top_muxes),
 	.flags = CLK_PARENT_TOPCKGEN,
+	.type = MTK_CLK_TREE_TOPCKGEN,
 };
 
 static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {
@@ -559,6 +561,12 @@ static const struct mtk_clk_tree mt7986_infracfg_clk_tree = {
 	.num_muxes = ARRAY_SIZE(infra_muxes),
 	.num_gates = ARRAY_SIZE(infracfg_gates),
 	.flags = CLK_PARENT_INFRASYS,
+	.type = MTK_CLK_TREE_INFRASYS,
+};
+
+static const struct mtk_clk_tree mt7986_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
 };
 
 static const struct udevice_id mt7986_fixed_pll_compat[] = {
@@ -587,20 +595,22 @@ static int mt7986_topckgen_probe(struct udevice *dev)
 	return mtk_common_clk_init(dev, &mt7986_topckgen_clk_tree);
 }
 
-U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+U_BOOT_DRIVER(mt7986_clk_apmixedsys) = {
 	.name = "mt7986-clock-fixed-pll",
 	.id = UCLASS_CLK,
 	.of_match = mt7986_fixed_pll_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7986_fixed_pll_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_fixed_pll_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_topckgen) = {
+U_BOOT_DRIVER(mt7986_clk_topckgen) = {
 	.name = "mt7986-clock-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt7986_topckgen_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7986_topckgen_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
@@ -614,13 +624,14 @@ static const struct udevice_id mt7986_infracfg_compat[] = {
 
 static int mt7986_infracfg_probe(struct udevice *dev)
 {
-	return mtk_common_clk_infrasys_init(dev, &mt7986_infracfg_clk_tree);
+	return mtk_common_clk_init(dev, &mt7986_infracfg_clk_tree);
 }
 
-U_BOOT_DRIVER(mtk_clk_infracfg) = {
+U_BOOT_DRIVER(mt7986_clk_infracfg) = {
 	.name = "mt7986-clock-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7986_infracfg_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7986_infracfg_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
@@ -649,7 +660,7 @@ static const struct mtk_gate eth_cgs[] = {
 
 static int mt7986_ethsys_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7986_topckgen_clk_tree, eth_cgs,
+	return mtk_common_clk_gate_init(dev, &mt7986_clk_tree, eth_cgs,
 					ARRAY_SIZE(eth_cgs), 0);
 }
 
@@ -671,7 +682,7 @@ static const struct udevice_id mt7986_ethsys_compat[] = {
 	{ }
 };
 
-U_BOOT_DRIVER(mtk_clk_ethsys) = {
+U_BOOT_DRIVER(mt7986_clk_ethsys) = {
 	.name = "mt7986-clock-ethsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7986_ethsys_compat,
diff --git a/drivers/clk/mediatek/clk-mt7987.c b/drivers/clk/mediatek/clk-mt7987.c
index 5f102636079..4ac0c6faa94 100644
--- a/drivers/clk/mediatek/clk-mt7987.c
+++ b/drivers/clk/mediatek/clk-mt7987.c
@@ -60,6 +60,7 @@ static const struct mtk_clk_tree mt7987_fixed_pll_clk_tree = {
 	.fclks = apmixedsys_mtk_plls,
 	.num_fclks = ARRAY_SIZE(apmixedsys_mtk_plls),
 	.flags = CLK_PARENT_APMIXED,
+	.type = MTK_CLK_TREE_APMIXED,
 };
 
 static const struct udevice_id mt7987_fixed_pll_compat[] = {
@@ -73,10 +74,11 @@ static int mt7987_fixed_pll_probe(struct udevice *dev)
 	return mtk_common_clk_init(dev, &mt7987_fixed_pll_clk_tree);
 }
 
-U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+U_BOOT_DRIVER(mt7987_clk_apmixedsys) = {
 	.name = "mt7987-clock-fixed-pll",
 	.id = UCLASS_CLK,
 	.of_match = mt7987_fixed_pll_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7987_fixed_pll_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_fixed_pll_ops,
@@ -457,6 +459,12 @@ static const struct mtk_clk_tree mt7987_topckgen_clk_tree = {
 	.num_fdivs = ARRAY_SIZE(topckgen_mtk_fixed_factors),
 	.num_muxes = ARRAY_SIZE(topckgen_mtk_muxes),
 	.flags = CLK_PARENT_TOPCKGEN,
+	.type = MTK_CLK_TREE_TOPCKGEN,
+};
+
+static const struct mtk_clk_tree mt7987_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
 };
 
 static const struct udevice_id mt7987_topckgen_compat[] = {
@@ -476,10 +484,11 @@ static int mt7987_topckgen_probe(struct udevice *dev)
 	return mtk_common_clk_init(dev, &mt7987_topckgen_clk_tree);
 }
 
-U_BOOT_DRIVER(mtk_clk_topckgen) = {
+U_BOOT_DRIVER(mt7987_clk_topckgen) = {
 	.name = "mt7987-clock-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt7987_topckgen_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7987_topckgen_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
@@ -783,6 +792,7 @@ static const struct mtk_clk_tree mt7987_infracfg_clk_tree = {
 	.gates = infracfg_mtk_gates,
 	.num_muxes = ARRAY_SIZE(infracfg_mtk_mux),
 	.num_gates = ARRAY_SIZE(infracfg_mtk_gates),
+	.type = MTK_CLK_TREE_INFRASYS,
 };
 
 static const struct udevice_id mt7987_infracfg_compat[] = {
@@ -793,13 +803,14 @@ static const struct udevice_id mt7987_infracfg_compat[] = {
 
 static int mt7987_infracfg_probe(struct udevice *dev)
 {
-	return mtk_common_clk_infrasys_init(dev, &mt7987_infracfg_clk_tree);
+	return mtk_common_clk_init(dev, &mt7987_infracfg_clk_tree);
 }
 
-U_BOOT_DRIVER(mtk_clk_infracfg) = {
+U_BOOT_DRIVER(mt7987_clk_infracfg) = {
 	.name = "mt7987-clock-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7987_infracfg_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7987_infracfg_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
@@ -829,7 +840,7 @@ static const struct mtk_gate eth_cgs[] = {
 
 static int mt7987_ethsys_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7987_topckgen_clk_tree, eth_cgs,
+	return mtk_common_clk_gate_init(dev, &mt7987_clk_tree, eth_cgs,
 					ARRAY_SIZE(eth_cgs), 0);
 }
 
@@ -853,7 +864,7 @@ static const struct udevice_id mt7987_ethsys_compat[] = {
 	{}
 };
 
-U_BOOT_DRIVER(mtk_clk_ethsys) = {
+U_BOOT_DRIVER(mt7987_clk_ethsys) = {
 	.name = "mt7987-clock-ethsys",
 	.id = UCLASS_CLK,
 	.of_match = mt7987_ethsys_compat,
diff --git a/drivers/clk/mediatek/clk-mt7988.c b/drivers/clk/mediatek/clk-mt7988.c
index 4e19f285da0..ebad78a9151 100644
--- a/drivers/clk/mediatek/clk-mt7988.c
+++ b/drivers/clk/mediatek/clk-mt7988.c
@@ -808,6 +808,7 @@ static const struct mtk_clk_tree mt7988_fixed_pll_clk_tree = {
 	.fclks = apmixedsys_mtk_plls,
 	.num_fclks = ARRAY_SIZE(apmixedsys_mtk_plls),
 	.flags = CLK_PARENT_APMIXED,
+	.type = MTK_CLK_TREE_APMIXED,
 };
 
 static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {
@@ -822,6 +823,7 @@ static const struct mtk_clk_tree mt7988_topckgen_clk_tree = {
 	.num_fdivs = ARRAY_SIZE(topckgen_mtk_fixed_factors),
 	.num_muxes = ARRAY_SIZE(topckgen_mtk_muxes),
 	.flags = CLK_PARENT_TOPCKGEN,
+	.type = MTK_CLK_TREE_TOPCKGEN,
 };
 
 static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {
@@ -833,6 +835,12 @@ static const struct mtk_clk_tree mt7988_infracfg_clk_tree = {
 	.gates = infracfg_mtk_gates,
 	.num_muxes = ARRAY_SIZE(infracfg_mtk_mux),
 	.num_gates = ARRAY_SIZE(infracfg_mtk_gates),
+	.type = MTK_CLK_TREE_INFRASYS,
+};
+
+static const struct mtk_clk_tree mt7988_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
 };
 
 static const struct udevice_id mt7988_fixed_pll_compat[] = {
@@ -863,20 +871,22 @@ static int mt7988_topckgen_probe(struct udevice *dev)
 	return mtk_common_clk_init(dev, &mt7988_topckgen_clk_tree);
 }
 
-U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+U_BOOT_DRIVER(mt7988_clk_apmixedsys) = {
 	.name = "mt7988-clock-fixed-pll",
 	.id = UCLASS_CLK,
 	.of_match = mt7988_fixed_pll_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7988_fixed_pll_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_fixed_pll_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_topckgen) = {
+U_BOOT_DRIVER(mt7988_clk_topckgen) = {
 	.name = "mt7988-clock-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt7988_topckgen_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7988_topckgen_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
@@ -890,13 +900,14 @@ static const struct udevice_id mt7988_infracfg_compat[] = {
 
 static int mt7988_infracfg_probe(struct udevice *dev)
 {
-	return mtk_common_clk_infrasys_init(dev, &mt7988_infracfg_clk_tree);
+	return mtk_common_clk_init(dev, &mt7988_infracfg_clk_tree);
 }
 
-U_BOOT_DRIVER(mtk_clk_infracfg) = {
+U_BOOT_DRIVER(mt7988_clk_infracfg) = {
 	.name = "mt7988-clock-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt7988_infracfg_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt7988_infracfg_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
@@ -924,8 +935,7 @@ static const struct mtk_gate ethdma_mtk_gate[] = {
 
 static int mt7988_ethdma_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
-					ethdma_mtk_gate,
+	return mtk_common_clk_gate_init(dev, &mt7988_clk_tree, ethdma_mtk_gate,
 					ARRAY_SIZE(ethdma_mtk_gate), 0);
 }
 
@@ -949,7 +959,7 @@ static const struct udevice_id mt7988_ethdma_compat[] = {
 	{}
 };
 
-U_BOOT_DRIVER(mtk_clk_ethdma) = {
+U_BOOT_DRIVER(mt7988_clk_ethdma) = {
 	.name = "mt7988-clock-ethdma",
 	.id = UCLASS_CLK,
 	.of_match = mt7988_ethdma_compat,
@@ -983,7 +993,7 @@ static const struct mtk_gate sgmiisys_0_mtk_gate[] = {
 
 static int mt7988_sgmiisys_0_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
+	return mtk_common_clk_gate_init(dev, &mt7988_clk_tree,
 					sgmiisys_0_mtk_gate,
 					ARRAY_SIZE(sgmiisys_0_mtk_gate), 0);
 }
@@ -995,7 +1005,7 @@ static const struct udevice_id mt7988_sgmiisys_0_compat[] = {
 	{}
 };
 
-U_BOOT_DRIVER(mtk_clk_sgmiisys_0) = {
+U_BOOT_DRIVER(mt7988_clk_sgmiisys_0) = {
 	.name = "mt7988-clock-sgmiisys_0",
 	.id = UCLASS_CLK,
 	.of_match = mt7988_sgmiisys_0_compat,
@@ -1028,7 +1038,7 @@ static const struct mtk_gate sgmiisys_1_mtk_gate[] = {
 
 static int mt7988_sgmiisys_1_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
+	return mtk_common_clk_gate_init(dev, &mt7988_clk_tree,
 					sgmiisys_1_mtk_gate,
 					ARRAY_SIZE(sgmiisys_1_mtk_gate), 0);
 }
@@ -1040,7 +1050,7 @@ static const struct udevice_id mt7988_sgmiisys_1_compat[] = {
 	{}
 };
 
-U_BOOT_DRIVER(mtk_clk_sgmiisys_1) = {
+U_BOOT_DRIVER(mt7988_clk_sgmiisys_1) = {
 	.name = "mt7988-clock-sgmiisys_1",
 	.id = UCLASS_CLK,
 	.of_match = mt7988_sgmiisys_1_compat,
@@ -1075,7 +1085,7 @@ static const struct mtk_gate ethwarp_mtk_gate[] = {
 
 static int mt7988_ethwarp_probe(struct udevice *dev)
 {
-	return mtk_common_clk_gate_init(dev, &mt7988_topckgen_clk_tree,
+	return mtk_common_clk_gate_init(dev, &mt7988_clk_tree,
 					ethwarp_mtk_gate,
 					ARRAY_SIZE(ethwarp_mtk_gate), 0);
 }
@@ -1100,7 +1110,7 @@ static const struct udevice_id mt7988_ethwarp_compat[] = {
 	{}
 };
 
-U_BOOT_DRIVER(mtk_clk_ethwarp) = {
+U_BOOT_DRIVER(mt7988_clk_ethwarp) = {
 	.name = "mt7988-clock-ethwarp",
 	.id = UCLASS_CLK,
 	.of_match = mt7988_ethwarp_compat,
diff --git a/drivers/clk/mediatek/clk-mt8183.c b/drivers/clk/mediatek/clk-mt8183.c
index 7b2d796bc6c..a619dce5ca3 100644
--- a/drivers/clk/mediatek/clk-mt8183.c
+++ b/drivers/clk/mediatek/clk-mt8183.c
@@ -604,20 +604,32 @@ static const struct mtk_composite top_muxes[] = {
 	MUX(CLK_TOP_MUX_AUD_2, aud_2_parents, 0xe0, 8, 1),
 };
 
-static const struct mtk_clk_tree mt8183_clk_tree = {
+static const struct mtk_clk_tree mt8183_apmixed_clk_tree = {
 	.pll_parent = EXT_PARENT(CLK_PAD_CLK26M),
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.plls = apmixed_plls,
+	.num_plls = ARRAY_SIZE(apmixed_plls),
+	.type = MTK_CLK_TREE_APMIXED,
+};
+
+static const struct mtk_clk_tree mt8183_topckgen_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
 	.fdivs_offs = CLK_TOP_CLK13M,
 	.muxes_offs = CLK_TOP_MUX_AXI,
-	.plls = apmixed_plls,
 	.fclks = top_fixed_clks,
 	.fdivs = top_fixed_divs,
 	.muxes = top_muxes,
-	.num_plls = ARRAY_SIZE(apmixed_plls),
 	.num_fclks = ARRAY_SIZE(top_fixed_clks),
 	.num_fdivs = ARRAY_SIZE(top_fixed_divs),
 	.num_muxes = ARRAY_SIZE(top_muxes),
+	.type = MTK_CLK_TREE_TOPCKGEN,
+};
+
+static const struct mtk_clk_tree mt8183_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
 };
 
 static const struct mtk_gate_regs infra0_cg_regs = {
@@ -782,12 +794,12 @@ static const struct mtk_gate infra_clks[] = {
 
 static int mt8183_apmixedsys_probe(struct udevice *dev)
 {
-	return mtk_common_clk_init(dev, &mt8183_clk_tree);
+	return mtk_common_clk_init(dev, &mt8183_apmixed_clk_tree);
 }
 
 static int mt8183_topckgen_probe(struct udevice *dev)
 {
-	return mtk_common_clk_init(dev, &mt8183_clk_tree);
+	return mtk_common_clk_init(dev, &mt8183_topckgen_clk_tree);
 }
 
 static int mt8183_infracfg_probe(struct udevice *dev)
@@ -811,27 +823,29 @@ static const struct udevice_id mt8183_infracfg_compat[] = {
 	{ }
 };
 
-U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+U_BOOT_DRIVER(mt8183_clk_apmixedsys) = {
 	.name = "mt8183-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt8183_apmixed_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt8183_apmixedsys_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_topckgen) = {
+U_BOOT_DRIVER(mt8183_clk_topckgen) = {
 	.name = "mt8183-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt8183_topckgen_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt8183_topckgen_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_infracfg) = {
+U_BOOT_DRIVER(mt8183_clk_infracfg) = {
 	.name = "mt8183-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt8183_infracfg_compat,
diff --git a/drivers/clk/mediatek/clk-mt8188.c b/drivers/clk/mediatek/clk-mt8188.c
index 3e413e111f1..f73fa1fce95 100644
--- a/drivers/clk/mediatek/clk-mt8188.c
+++ b/drivers/clk/mediatek/clk-mt8188.c
@@ -89,6 +89,7 @@ static const struct mtk_clk_tree mt8188_apmixedsys_clk_tree = {
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
 	.plls = apmixed_plls,
 	.num_plls = ARRAY_SIZE(apmixed_plls),
+	.type = MTK_CLK_TREE_APMIXED,
 };
 
 #define FIXED_CLK0(_id, _rate)			\
@@ -1422,6 +1423,7 @@ static const struct mtk_clk_tree mt8188_topckgen_clk_tree = {
 	.num_fdivs = ARRAY_SIZE(top_fixed_divs),
 	.num_muxes = ARRAY_SIZE(top_muxes),
 	.num_gates = ARRAY_SIZE(topckgen_cg_clks),
+	.type = MTK_CLK_TREE_TOPCKGEN,
 };
 
 static const struct mtk_gate_regs infra_ao0_cg_regs = {
@@ -1657,6 +1659,7 @@ static const struct mtk_gate pericfg_ao_clks[] = {
 	GATE_PERI_AO(CLK_PERI_AO_SSUSB_BUS, CLK_TOP_USB_TOP, 13),
 	GATE_PERI_AO(CLK_PERI_AO_SSUSB_XHCI, CLK_TOP_SSUSB_XHCI, 14),
 	GATE_PERI_AO(CLK_PERI_AO_ETHERNET_MAC, CLK_TOP_SNPS_ETH_250M, 16),
+	GATE_PERI_AO(CLK_PERI_AO_PCIE_P0_FMEM, CLK_TOP_466M_FMEM, 24),
 };
 
 static const struct mtk_clk_tree mt8188_pericfg_ao_clk_tree = {
@@ -1789,27 +1792,29 @@ static const struct udevice_id mt8188_imp_iic_wrap_en_compat[] = {
 	{ }
 };
 
-U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+U_BOOT_DRIVER(mt8188_clk_apmixedsys) = {
 	.name = "mt8188-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt8188_apmixed_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt8188_apmixedsys_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_topckgen) = {
+U_BOOT_DRIVER(mt8188_clk_topckgen) = {
 	.name = "mt8188-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt8188_topckgen_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt8188_topckgen_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_infracfg_ao) = {
+U_BOOT_DRIVER(mt8188_clk_infracfg_ao) = {
 	.name = "mt8188-infracfg-ao",
 	.id = UCLASS_CLK,
 	.of_match = mt8188_infracfg_ao_compat,
@@ -1819,7 +1824,7 @@ U_BOOT_DRIVER(mtk_clk_infracfg_ao) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_pericfg_ao) = {
+U_BOOT_DRIVER(mt8188_clk_pericfg_ao) = {
 	.name = "mt8188-pericfg-ao",
 	.id = UCLASS_CLK,
 	.of_match = mt8188_pericfg_ao_compat,
@@ -1829,7 +1834,7 @@ U_BOOT_DRIVER(mtk_clk_pericfg_ao) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_imp_iic_wrap_c) = {
+U_BOOT_DRIVER(mt8188_clk_imp_iic_wrap_c) = {
 	.name = "mt8188-imp_iic_wrap_c",
 	.id = UCLASS_CLK,
 	.of_match = mt8188_imp_iic_wrap_c_compat,
@@ -1839,7 +1844,7 @@ U_BOOT_DRIVER(mtk_clk_imp_iic_wrap_c) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_imp_iic_wrap_w) = {
+U_BOOT_DRIVER(mt8188_clk_imp_iic_wrap_w) = {
 	.name = "mt8188-imp_iic_wrap_w",
 	.id = UCLASS_CLK,
 	.of_match = mt8188_imp_iic_wrap_w_compat,
@@ -1849,7 +1854,7 @@ U_BOOT_DRIVER(mtk_clk_imp_iic_wrap_w) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_imp_iic_wrap_en) = {
+U_BOOT_DRIVER(mt8188_clk_imp_iic_wrap_en) = {
 	.name = "mt8188-imp_iic_wrap_en",
 	.id = UCLASS_CLK,
 	.of_match = mt8188_imp_iic_wrap_en_compat,
diff --git a/drivers/clk/mediatek/clk-mt8189.c b/drivers/clk/mediatek/clk-mt8189.c
index d11947ee461..3093fac23ce 100644
--- a/drivers/clk/mediatek/clk-mt8189.c
+++ b/drivers/clk/mediatek/clk-mt8189.c
@@ -1898,6 +1898,7 @@ static const struct mtk_gate_regs vlpcfg_ao_regs = {
  * arbitrary parent trees.
  */
 #define CLK_PARENT_VLP_CK CLK_PARENT_INFRASYS
+#define MTK_CLK_TREE_VLP_CK MTK_CLK_TREE_INFRASYS
 
 #define GATE_VLPCFG_AO(id, parent, shift, flags) \
 	GATE_FLAGS(id, parent, &vlpcfg_ao_regs, shift, flags | CLK_GATE_NO_SETCLR_INV)
@@ -1915,8 +1916,8 @@ static const struct mtk_gate vlpcfg_ao_clks[] = {
 	GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SCP, CLK_VLP_CK_SCP_SEL, 28),
 	GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_RG_R_APXGPT_26M, CLK_PAD_CLK26M, 24),
 	GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_DPMSRCK_TEST, CLK_PAD_CLK26M, 23),
-	GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_RG_DPMSRRTC_TEST, CLK_PAD_CLK32K, 22),
-	GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_DPMSRULP_TEST, CLK_TOP_OSC_D10, 21),
+	GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_RG_DPMSRRTC_TEST, CLK_PAD_CLK32K, 22),
+	GATE_VLPCFG_AO_TOP(CLK_VLPCFG_REG_DPMSRULP_TEST, CLK_TOP_OSC_D10, 21),
 	GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_SPMI_P_MST, CLK_VLP_CK_SPMI_P_MST_SEL, 20),
 	GATE_VLPCFG_AO_EXT(CLK_VLPCFG_REG_SPMI_P_MST_32K, CLK_PAD_CLK32K, 18),
 	GATE_VLPCFG_AO_VLP(CLK_VLPCFG_REG_PMIF_SPMI_P_SYS, CLK_VLP_CK_PWRAP_ULPOSC_SEL, 13),
@@ -1939,6 +1940,7 @@ static const struct mtk_clk_tree mt8189_apmixedsys_clk_tree = {
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
 	.plls = apmixed_plls,
 	.num_plls = ARRAY_SIZE(apmixed_plls),
+	.type = MTK_CLK_TREE_APMIXED,
 };
 
 static const struct mtk_clk_tree mt8189_topckgen_clk_tree = {
@@ -1953,6 +1955,7 @@ static const struct mtk_clk_tree mt8189_topckgen_clk_tree = {
 	.num_fdivs = ARRAY_SIZE(top_fixed_divs),
 	.num_muxes = ARRAY_SIZE(top_muxes),
 	.num_gates = ARRAY_SIZE(top_gates),
+	.type = MTK_CLK_TREE_TOPCKGEN,
 };
 
 static const struct mtk_clk_tree mt8189_vlpckgen_clk_tree = {
@@ -1964,6 +1967,12 @@ static const struct mtk_clk_tree mt8189_vlpckgen_clk_tree = {
 	.gates = vlp_ck_gates,
 	.num_muxes = ARRAY_SIZE(vlp_ck_muxes),
 	.num_gates = ARRAY_SIZE(vlp_ck_gates),
+	.type = MTK_CLK_TREE_VLP_CK,
+};
+
+static const struct mtk_clk_tree mt8189_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
 };
 
 static const struct udevice_id mt8189_apmixed[] = {
@@ -2022,7 +2031,7 @@ static int mt8189_topckgen_probe(struct udevice *dev)
 
 static int mt8189_infrasys_probe(struct udevice *dev)
 {
-	return mtk_common_clk_infrasys_init(dev, &mt8189_vlpckgen_clk_tree);
+	return mtk_common_clk_init(dev, &mt8189_vlpckgen_clk_tree);
 }
 
 static int mt8189_clk_gate_probe(struct udevice *dev)
@@ -2031,42 +2040,45 @@ static int mt8189_clk_gate_probe(struct udevice *dev)
 
 	data = (void *)dev_get_driver_data(dev);
 
-	return mtk_common_clk_gate_init(dev, &mt8189_topckgen_clk_tree,
+	return mtk_common_clk_gate_init(dev, &mt8189_clk_tree,
 					data->gates, data->num_gates,
 					data->gates[0].id);
 }
 
-U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+U_BOOT_DRIVER(mt8189_clk_apmixedsys) = {
 	.name = "mt8189-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt8189_apmixed,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt8189_apmixedsys_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_topckgen) = {
+U_BOOT_DRIVER(mt8189_clk_topckgen) = {
 	.name = "mt8189-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt8189_topckgen_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt8189_topckgen_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_vlpckgen) = {
+U_BOOT_DRIVER(mt8189_clk_vlpckgen) = {
 	.name = "mt8189-vlpckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt8189_vlpckgen,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt8189_infrasys_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_infrasys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_gate) = {
+U_BOOT_DRIVER(mt8189_clk_gate) = {
 	.name = "mt8189-gate-clk",
 	.id = UCLASS_CLK,
 	.of_match = of_match_mt8189_clk_gate,
diff --git a/drivers/clk/mediatek/clk-mt8195.c b/drivers/clk/mediatek/clk-mt8195.c
index 37cceb5f32b..c12463cc616 100644
--- a/drivers/clk/mediatek/clk-mt8195.c
+++ b/drivers/clk/mediatek/clk-mt8195.c
@@ -101,6 +101,7 @@ static const struct mtk_clk_tree mt8195_apmixedsys_clk_tree = {
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
 	.plls = apmixed_plls,
 	.num_plls = ARRAY_SIZE(apmixed_plls),
+	.type = MTK_CLK_TREE_APMIXED,
 };
 
 #define FIXED_CLK0(_id, _rate)	\
@@ -1423,6 +1424,7 @@ static const struct mtk_clk_tree mt8195_topckgen_clk_tree = {
 	.num_fdivs = ARRAY_SIZE(top_fixed_divs),
 	.num_muxes = ARRAY_SIZE(top_muxes),
 	.num_gates = ARRAY_SIZE(top_cg_clks),
+	.type = MTK_CLK_TREE_TOPCKGEN,
 };
 
 static const struct mtk_gate_regs infra_ao0_cg_regs = {
@@ -1631,27 +1633,29 @@ static const struct udevice_id of_match_clk_mt8195_infra_ao[] = {
 	{ }
 };
 
-U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+U_BOOT_DRIVER(mt8195_clk_apmixedsys) = {
 	.name = "mt8195-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt8195_apmixed,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt8195_apmixedsys_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_topckgen) = {
+U_BOOT_DRIVER(mt8195_clk_topckgen) = {
 	.name = "mt8195-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt8195_topckgen_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt8195_topckgen_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_infra_ao) = {
+U_BOOT_DRIVER(mt8195_clk_infra_ao) = {
 	.name = "mt8195-infra_ao",
 	.id = UCLASS_CLK,
 	.of_match = of_match_clk_mt8195_infra_ao,
diff --git a/drivers/clk/mediatek/clk-mt8365.c b/drivers/clk/mediatek/clk-mt8365.c
index eb94b86622c..bb00d6154e1 100644
--- a/drivers/clk/mediatek/clk-mt8365.c
+++ b/drivers/clk/mediatek/clk-mt8365.c
@@ -79,6 +79,7 @@ static const struct mtk_clk_tree mt8365_apmixed_tree = {
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
 	.plls = apmixed_plls,
 	.num_plls = ARRAY_SIZE(apmixed_plls),
+	.type = MTK_CLK_TREE_APMIXED,
 };
 
 /* topckgen */
@@ -595,6 +596,7 @@ static const struct mtk_clk_tree mt8365_topckgen_tree = {
 	.num_fdivs = ARRAY_SIZE(top_divs),
 	.num_muxes = ARRAY_SIZE(top_muxes),
 	.num_gates = ARRAY_SIZE(top_clk_gates),
+	.type = MTK_CLK_TREE_TOPCKGEN,
 };
 
 /* infracfg */
@@ -788,27 +790,29 @@ static const struct udevice_id mt8365_infracfg_compat[] = {
 	{ }
 };
 
-U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+U_BOOT_DRIVER(mt8365_clk_apmixedsys) = {
 	.name = "mt8365-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt8365_apmixed_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt8365_apmixedsys_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_topckgen) = {
+U_BOOT_DRIVER(mt8365_clk_topckgen) = {
 	.name = "mt8365-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt8365_topckgen_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt8365_topckgen_probe,
 	.priv_auto = sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_infracfg) = {
+U_BOOT_DRIVER(mt8365_clk_infracfg) = {
 	.name = "mt8365-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt8365_infracfg_compat,
diff --git a/drivers/clk/mediatek/clk-mt8512.c b/drivers/clk/mediatek/clk-mt8512.c
index d6e58be8e22..88c55e5ac6c 100644
--- a/drivers/clk/mediatek/clk-mt8512.c
+++ b/drivers/clk/mediatek/clk-mt8512.c
@@ -792,30 +792,42 @@ static const struct mtk_gate infra_clks[] = {
 	GATE_INFRA5(CLK_INFRA_USB_XHCI, CLK_TOP_SSUSB_XHCI_SEL, 11),
 };
 
-static const struct mtk_clk_tree mt8512_clk_tree = {
+static const struct mtk_clk_tree mt8512_apmixed_clk_tree = {
 	.pll_parent = EXT_PARENT(CLK_PAD_CLK26M),
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.plls = apmixed_plls,
+	.num_plls = ARRAY_SIZE(apmixed_plls),
+	.type = MTK_CLK_TREE_APMIXED,
+};
+
+static const struct mtk_clk_tree mt8512_topckgen_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
 	.fdivs_offs = CLK_TOP_SYSPLL1_D2,
 	.muxes_offs = CLK_TOP_AXI_SEL,
-	.plls = apmixed_plls,
 	.fclks = top_fixed_clks,
 	.fdivs = top_fixed_divs,
 	.muxes = top_muxes,
-	.num_plls = ARRAY_SIZE(apmixed_plls),
 	.num_fclks = ARRAY_SIZE(top_fixed_clks),
 	.num_fdivs = ARRAY_SIZE(top_fixed_divs),
 	.num_muxes = ARRAY_SIZE(top_muxes),
+	.type = MTK_CLK_TREE_TOPCKGEN,
+};
+
+static const struct mtk_clk_tree mt8512_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
 };
 
 static int mt8512_apmixedsys_probe(struct udevice *dev)
 {
-	return mtk_common_clk_init(dev, &mt8512_clk_tree);
+	return mtk_common_clk_init(dev, &mt8512_apmixed_clk_tree);
 }
 
 static int mt8512_topckgen_probe(struct udevice *dev)
 {
-	return mtk_common_clk_init(dev, &mt8512_clk_tree);
+	return mtk_common_clk_init(dev, &mt8512_topckgen_clk_tree);
 }
 
 static int mt8512_topckgen_cg_probe(struct udevice *dev)
@@ -850,27 +862,29 @@ static const struct udevice_id mt8512_infracfg_compat[] = {
 	{ }
 };
 
-U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+U_BOOT_DRIVER(mt8512_clk_apmixedsys) = {
 	.name = "mt8512-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt8512_apmixed_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt8512_apmixedsys_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_topckgen) = {
+U_BOOT_DRIVER(mt8512_clk_topckgen) = {
 	.name = "mt8512-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt8512_topckgen_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt8512_topckgen_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
+U_BOOT_DRIVER(mt8512_clk_topckgen_cg) = {
 	.name = "mt8512-topckgen-cg",
 	.id = UCLASS_CLK,
 	.of_match = mt8512_topckgen_cg_compat,
@@ -880,7 +894,7 @@ U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_infracfg) = {
+U_BOOT_DRIVER(mt8512_clk_infracfg) = {
 	.name = "mt8512-infracfg",
 	.id = UCLASS_CLK,
 	.of_match = mt8512_infracfg_compat,
diff --git a/drivers/clk/mediatek/clk-mt8516.c b/drivers/clk/mediatek/clk-mt8516.c
index 1070dd1551b..9c510005b42 100644
--- a/drivers/clk/mediatek/clk-mt8516.c
+++ b/drivers/clk/mediatek/clk-mt8516.c
@@ -744,30 +744,42 @@ static const struct mtk_gate top_clks[] = {
 	GATE_TOP5(CLK_TOP_APLL12_DIV6, CLK_TOP_APLL12_CK_DIV6, 8),
 };
 
-static const struct mtk_clk_tree mt8516_clk_tree = {
+static const struct mtk_clk_tree mt8516_apmixed_clk_tree = {
 	.pll_parent = EXT_PARENT(CLK_PAD_CLK26M),
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.plls = apmixed_plls,
+	.num_plls = ARRAY_SIZE(apmixed_plls),
+	.type = MTK_CLK_TREE_APMIXED,
+};
+
+static const struct mtk_clk_tree mt8516_topckgen_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
 	.fdivs_offs = CLK_TOP_DMPLL,
 	.muxes_offs = CLK_TOP_UART0_SEL,
-	.plls = apmixed_plls,
 	.fclks = top_fixed_clks,
 	.fdivs = top_fixed_divs,
 	.muxes = top_muxes,
-	.num_plls = ARRAY_SIZE(apmixed_plls),
 	.num_fclks = ARRAY_SIZE(top_fixed_clks),
 	.num_fdivs = ARRAY_SIZE(top_fixed_divs),
 	.num_muxes = ARRAY_SIZE(top_muxes),
+	.type = MTK_CLK_TREE_TOPCKGEN,
+};
+
+static const struct mtk_clk_tree mt8516_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
 };
 
 static int mt8516_apmixedsys_probe(struct udevice *dev)
 {
-	return mtk_common_clk_init(dev, &mt8516_clk_tree);
+	return mtk_common_clk_init(dev, &mt8516_apmixed_clk_tree);
 }
 
 static int mt8516_topckgen_probe(struct udevice *dev)
 {
-	return mtk_common_clk_init(dev, &mt8516_clk_tree);
+	return mtk_common_clk_init(dev, &mt8516_topckgen_clk_tree);
 }
 
 static int mt8516_topckgen_cg_probe(struct udevice *dev)
@@ -791,27 +803,29 @@ static const struct udevice_id mt8516_topckgen_cg_compat[] = {
 	{ }
 };
 
-U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+U_BOOT_DRIVER(mt8516_clk_apmixedsys) = {
 	.name = "mt8516-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt8516_apmixed_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt8516_apmixedsys_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_topckgen) = {
+U_BOOT_DRIVER(mt8516_clk_topckgen) = {
 	.name = "mt8516-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt8516_topckgen_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt8516_topckgen_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
+U_BOOT_DRIVER(mt8516_clk_topckgen_cg) = {
 	.name = "mt8516-topckgen-cg",
 	.id = UCLASS_CLK,
 	.of_match = mt8516_topckgen_cg_compat,
diff --git a/drivers/clk/mediatek/clk-mt8518.c b/drivers/clk/mediatek/clk-mt8518.c
index 2b213e720a0..1033ecae187 100644
--- a/drivers/clk/mediatek/clk-mt8518.c
+++ b/drivers/clk/mediatek/clk-mt8518.c
@@ -1500,30 +1500,42 @@ static const struct mtk_gate top_clks[] = {
 	GATE_TOP7(CLK_TOP_DISP_DPI, CLK_TOP_DISP_DPI_CK_SEL, 0),
 };
 
-static const struct mtk_clk_tree mt8518_clk_tree = {
+static const struct mtk_clk_tree mt8518_apmixed_clk_tree = {
 	.pll_parent = EXT_PARENT(CLK_PAD_CLK26M),
 	.ext_clk_rates = ext_clock_rates,
 	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
+	.plls = apmixed_plls,
+	.num_plls = ARRAY_SIZE(apmixed_plls),
+	.type = MTK_CLK_TREE_APMIXED,
+};
+
+static const struct mtk_clk_tree mt8518_topckgen_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
 	.fdivs_offs = CLK_TOP_DMPLL,
 	.muxes_offs = CLK_TOP_UART0_SEL,
-	.plls = apmixed_plls,
 	.fclks = top_fixed_clks,
 	.fdivs = top_fixed_divs,
 	.muxes = top_muxes,
-	.num_plls = ARRAY_SIZE(apmixed_plls),
 	.num_fclks = ARRAY_SIZE(top_fixed_clks),
 	.num_fdivs = ARRAY_SIZE(top_fixed_divs),
 	.num_muxes = ARRAY_SIZE(top_muxes),
+	.type = MTK_CLK_TREE_TOPCKGEN,
+};
+
+static const struct mtk_clk_tree mt8518_clk_tree = {
+	.ext_clk_rates = ext_clock_rates,
+	.num_ext_clks = ARRAY_SIZE(ext_clock_rates),
 };
 
 static int mt8518_apmixedsys_probe(struct udevice *dev)
 {
-	return mtk_common_clk_init(dev, &mt8518_clk_tree);
+	return mtk_common_clk_init(dev, &mt8518_apmixed_clk_tree);
 }
 
 static int mt8518_topckgen_probe(struct udevice *dev)
 {
-	return mtk_common_clk_init(dev, &mt8518_clk_tree);
+	return mtk_common_clk_init(dev, &mt8518_topckgen_clk_tree);
 }
 
 static int mt8518_topckgen_cg_probe(struct udevice *dev)
@@ -1547,27 +1559,29 @@ static const struct udevice_id mt8518_topckgen_cg_compat[] = {
 	{ }
 };
 
-U_BOOT_DRIVER(mtk_clk_apmixedsys) = {
+U_BOOT_DRIVER(mt8518_clk_apmixedsys) = {
 	.name = "mt8518-apmixedsys",
 	.id = UCLASS_CLK,
 	.of_match = mt8518_apmixed_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt8518_apmixedsys_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_apmixedsys_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_topckgen) = {
+U_BOOT_DRIVER(mt8518_clk_topckgen) = {
 	.name = "mt8518-topckgen",
 	.id = UCLASS_CLK,
 	.of_match = mt8518_topckgen_compat,
+	.bind = mtk_common_clk_parent_bind,
 	.probe = mt8518_topckgen_probe,
 	.priv_auto	= sizeof(struct mtk_clk_priv),
 	.ops = &mtk_clk_topckgen_ops,
 	.flags = DM_FLAG_PRE_RELOC,
 };
 
-U_BOOT_DRIVER(mtk_clk_topckgen_cg) = {
+U_BOOT_DRIVER(mt8518_clk_topckgen_cg) = {
 	.name = "mt8518-topckgen-cg",
 	.id = UCLASS_CLK,
 	.of_match = mt8518_topckgen_cg_compat,
diff --git a/drivers/clk/mediatek/clk-mtk.c b/drivers/clk/mediatek/clk-mtk.c
index 9d0a6cd79cf..61d718f162d 100644
--- a/drivers/clk/mediatek/clk-mtk.c
+++ b/drivers/clk/mediatek/clk-mtk.c
@@ -34,6 +34,54 @@
 #define SCP_AXICK_DCM_DIS_EN		BIT(0)
 #define SCP_AXICK_26M_SEL_EN		BIT(4)
 
+static struct udevice *mtk_clk_providers[MTK_CLK_TREE_NUM_TYPES];
+
+static bool mtk_clk_tree_type_is_provider(enum mtk_clk_tree_type type)
+{
+	return type != MTK_CLK_TREE_NONE && type < MTK_CLK_TREE_NUM_TYPES;
+}
+
+static enum mtk_clk_tree_type mtk_clk_tree_type_from_parent_flags(u16 flags)
+{
+	switch (flags & CLK_PARENT_MASK) {
+	case CLK_PARENT_APMIXED:
+		return MTK_CLK_TREE_APMIXED;
+	case CLK_PARENT_TOPCKGEN:
+		return MTK_CLK_TREE_TOPCKGEN;
+	case CLK_PARENT_INFRASYS:
+		return MTK_CLK_TREE_INFRASYS;
+	default:
+		return MTK_CLK_TREE_NONE;
+	}
+}
+
+static struct udevice *mtk_clk_tree_get_provider(enum mtk_clk_tree_type type)
+{
+	if (!mtk_clk_tree_type_is_provider(type))
+		return NULL;
+
+	return mtk_clk_providers[type] ?: ERR_PTR(-ENOENT);
+}
+
+static struct udevice *mtk_clk_parent_get_provider(u16 flags)
+{
+	return mtk_clk_tree_get_provider(mtk_clk_tree_type_from_parent_flags(flags));
+}
+
+static int mtk_clk_tree_register_provider(struct udevice *dev,
+					  const struct mtk_clk_tree *tree)
+{
+	if (!mtk_clk_tree_type_is_provider(tree->type))
+		return 0;
+
+	if (mtk_clk_providers[tree->type])
+		return -EEXIST;
+
+	mtk_clk_providers[tree->type] = dev;
+
+	return 0;
+}
+
 /* shared functions */
 
 static const int mtk_common_clk_of_xlate(struct clk *clk,
@@ -207,50 +255,16 @@ static ulong mtk_clk_find_parent_rate(struct clk *clk, int id,
 static ulong mtk_find_parent_rate(struct mtk_clk_priv *priv, struct clk *clk,
 				  const int parent, u16 flags)
 {
-	struct udevice *parent_dev;
-
-	switch (flags & CLK_PARENT_MASK) {
-	case CLK_PARENT_APMIXED:
-		/* APMIXEDSYS can be parent or grandparent. */
-		if (dev_get_driver_ops(clk->dev) == &mtk_clk_apmixedsys_ops ||
-		    dev_get_driver_ops(clk->dev) == &mtk_clk_fixed_pll_ops) {
-			parent_dev = clk->dev;
-		} else if (dev_get_driver_ops(priv->parent) == &mtk_clk_apmixedsys_ops ||
-			   dev_get_driver_ops(priv->parent) == &mtk_clk_fixed_pll_ops) {
-			parent_dev = priv->parent;
-		} else {
-			struct udevice *grandparent_dev = dev_get_parent(priv->parent);
+	struct udevice *pdev;
 
-			if (dev_get_driver_ops(grandparent_dev) == &mtk_clk_apmixedsys_ops ||
-			    dev_get_driver_ops(grandparent_dev) == &mtk_clk_fixed_pll_ops)
-				parent_dev = grandparent_dev;
-			else
-				return -EINVAL;
-		}
-		break;
-	case CLK_PARENT_TOPCKGEN:
-		if (dev_get_driver_ops(clk->dev) == &mtk_clk_topckgen_ops)
-			parent_dev = clk->dev;
-		else if (dev_get_driver_ops(priv->parent) == &mtk_clk_topckgen_ops)
-			parent_dev = priv->parent;
-		else
-			return -EINVAL;
-
-		break;
-	case CLK_PARENT_INFRASYS:
-		if (dev_get_driver_ops(clk->dev) != &mtk_clk_infrasys_ops)
-			return -EINVAL;
-
-		parent_dev = clk->dev;
-		break;
-	case CLK_PARENT_EXT:
+	if ((flags & CLK_PARENT_MASK) == CLK_PARENT_EXT)
 		return mtk_ext_clock_get_rate(priv->tree, parent);
-	default:
-		parent_dev = NULL;
-		break;
-	}
 
-	return mtk_clk_find_parent_rate(clk, parent, parent_dev);
+	pdev = mtk_clk_parent_get_provider(flags);
+	if (IS_ERR(pdev))
+		return PTR_ERR(pdev);
+
+	return mtk_clk_find_parent_rate(clk, parent, pdev);
 }
 
 static ulong mtk_clk_mux_get_rate(struct clk *clk, u32 off)
@@ -306,11 +320,6 @@ static int mtk_clk_mux_set_parent(void __iomem *base, u32 parent,
 }
 
 #if CONFIG_IS_ENABLED(CMD_CLK)
-static void mtk_clk_print_dev_parent(struct udevice *parent)
-{
-	printf("Parent device: %s %s\n", parent->driver->name, parent->name);
-}
-
 static void mtk_clk_print_mapped_id(int unmapped_id, int mapped_id, bool has_map)
 {
 	/*
@@ -663,8 +672,6 @@ static void mtk_apmixedsys_dump(struct udevice *dev)
 	const struct mtk_clk_tree *tree = priv->tree;
 	u32 i;
 
-	mtk_clk_print_dev_parent(priv->parent);
-
 	for (i = 0; i < tree->num_plls; i++) {
 		const struct mtk_pll_data *pll = &tree->plls[i];
 
@@ -869,8 +876,6 @@ static void mtk_topckgen_dump(struct udevice *dev)
 	const struct mtk_clk_tree *tree = priv->tree;
 	u32 i;
 
-	mtk_clk_print_dev_parent(priv->parent);
-
 	for (i = 0; i < tree->num_fclks; i++) {
 		const struct mtk_fixed_clk *fclk = &tree->fclks[i];
 
@@ -1005,8 +1010,6 @@ static void mtk_infrasys_dump(struct udevice *dev)
 	const struct mtk_clk_tree *tree = priv->tree;
 	u32 i;
 
-	mtk_clk_print_dev_parent(priv->parent);
-
 	for (i = 0; i < tree->num_fdivs; i++) {
 		const struct mtk_fixed_factor *fdiv = &tree->fdivs[i];
 
@@ -1083,29 +1086,22 @@ static int mtk_clk_gate_disable(struct clk *clk)
 static ulong mtk_clk_gate_get_rate(struct clk *clk)
 {
 	struct mtk_cg_priv *priv = dev_get_priv(clk->dev);
-	struct udevice *parent = priv->parent;
 	const struct mtk_gate *gate;
+	struct udevice *pdev;
 
 	if (clk->id < priv->gates_offs)
 		return -EINVAL;
 
 	gate = &priv->gates[clk->id - priv->gates_offs];
-	/*
-	 * With requesting a TOPCKGEN parent, make sure the dev parent
-	 * is actually topckgen. This might not be the case for an
-	 * infracfg-ao implementation where:
-	 * parent = infracfg
-	 * parent->parent = topckgen
-	 */
-	if (gate->flags & CLK_PARENT_TOPCKGEN &&
-	    parent->driver != DM_DRIVER_GET(mtk_clk_topckgen)) {
-		priv = dev_get_priv(parent);
-		parent = priv->parent;
-	} else if (gate->flags & CLK_PARENT_EXT) {
+
+	if (gate->flags & CLK_PARENT_EXT)
 		return mtk_ext_clock_get_rate(priv->tree, gate->parent);
-	}
 
-	return mtk_clk_find_parent_rate(clk, gate->parent, parent);
+	pdev = mtk_clk_parent_get_provider(gate->flags);
+	if (IS_ERR(pdev))
+		return -ENOENT;
+
+	return mtk_clk_find_parent_rate(clk, gate->parent, pdev);
 }
 
 #if CONFIG_IS_ENABLED(CMD_CLK)
@@ -1115,8 +1111,6 @@ static void mtk_clk_gate_dump(struct udevice *dev)
 	const struct mtk_clk_tree *tree = priv->tree;
 	u32 i;
 
-	mtk_clk_print_dev_parent(priv->parent);
-
 	for (i = 0; i < priv->num_gates; i++) {
 		const struct mtk_gate *gate = &priv->gates[i];
 
@@ -1182,43 +1176,28 @@ const struct clk_ops mtk_clk_gate_ops = {
 #endif
 };
 
-static int mtk_common_clk_init_drv(struct udevice *dev,
-				   const struct mtk_clk_tree *tree,
-				   const struct driver *drv)
+int mtk_common_clk_parent_bind(struct udevice *dev)
+{
+	/*
+	 * Clock trees that provide parent clocks need to be probed right away
+	 * so that any clock depending on them will work correctly.
+	 */
+	dev_or_flags(dev, DM_FLAG_PROBE_AFTER_BIND);
+
+	return 0;
+}
+
+int mtk_common_clk_init(struct udevice *dev, const struct mtk_clk_tree *tree)
 {
 	struct mtk_clk_priv *priv = dev_get_priv(dev);
-	struct udevice *parent;
-	int ret;
 
 	priv->base = dev_read_addr_ptr(dev);
 	if (!priv->base)
 		return -ENOENT;
 
-	ret = uclass_get_device_by_phandle(UCLASS_CLK, dev, "clock-parent", &parent);
-	if (ret || !parent) {
-		ret = uclass_get_device_by_driver(UCLASS_CLK, drv, &parent);
-		if (ret || !parent)
-			return -ENOENT;
-	}
-
-	priv->parent = parent;
 	priv->tree = tree;
 
-	return 0;
-}
-
-int mtk_common_clk_init(struct udevice *dev,
-			const struct mtk_clk_tree *tree)
-{
-	return mtk_common_clk_init_drv(dev, tree,
-				       DM_DRIVER_GET(mtk_clk_apmixedsys));
-}
-
-int mtk_common_clk_infrasys_init(struct udevice *dev,
-				 const struct mtk_clk_tree *tree)
-{
-	return mtk_common_clk_init_drv(dev, tree,
-				       DM_DRIVER_GET(mtk_clk_topckgen));
+	return mtk_clk_tree_register_provider(dev, tree);
 }
 
 int mtk_common_clk_gate_init(struct udevice *dev,
@@ -1227,22 +1206,11 @@ int mtk_common_clk_gate_init(struct udevice *dev,
 			     int gates_offs)
 {
 	struct mtk_cg_priv *priv = dev_get_priv(dev);
-	struct udevice *parent;
-	int ret;
 
 	priv->base = dev_read_addr_ptr(dev);
 	if (!priv->base)
 		return -ENOENT;
 
-	ret = uclass_get_device_by_phandle(UCLASS_CLK, dev, "clock-parent", &parent);
-	if (ret || !parent) {
-		ret = uclass_get_device_by_driver(UCLASS_CLK,
-				DM_DRIVER_GET(mtk_clk_topckgen), &parent);
-		if (ret || !parent)
-			return -ENOENT;
-	}
-
-	priv->parent = parent;
 	priv->tree = tree;
 	priv->gates = gates;
 	priv->num_gates = num_gates;
diff --git a/drivers/clk/mediatek/clk-mtk.h b/drivers/clk/mediatek/clk-mtk.h
index b39a62edc43..437797dd0df 100644
--- a/drivers/clk/mediatek/clk-mtk.h
+++ b/drivers/clk/mediatek/clk-mtk.h
@@ -32,6 +32,15 @@
 
 #define ETHSYS_HIFSYS_RST_CTRL_OFS	0x34
 
+/* These get matched to CLK_PARENT_* when looking up parent clocks. */
+enum mtk_clk_tree_type {
+	MTK_CLK_TREE_NONE,
+	MTK_CLK_TREE_APMIXED,
+	MTK_CLK_TREE_TOPCKGEN,
+	MTK_CLK_TREE_INFRASYS,
+	MTK_CLK_TREE_NUM_TYPES
+};
+
 /* struct mtk_pll_data - hardware-specific PLLs data */
 struct mtk_pll_data {
 	/* unmapped ID of clock */
@@ -261,16 +270,21 @@ struct mtk_clk_tree {
 	const int num_muxes;
 	const int num_gates;
 	u32 flags;
+	/*
+	 * Set this if this tree provides a specific type for parent lookup.
+	 * Devices that set this should also include mtk_common_clk_parent_bind()
+	 * in the driver bind function to ensure that it will be registered as
+	 * a provider.
+	 */
+	enum mtk_clk_tree_type type;
 };
 
 struct mtk_clk_priv {
-	struct udevice *parent;
 	void __iomem *base;
 	const struct mtk_clk_tree *tree;
 };
 
 struct mtk_cg_priv {
-	struct udevice *parent;
 	void __iomem *base;
 	const struct mtk_clk_tree *tree;
 	const struct mtk_gate *gates;
@@ -284,10 +298,9 @@ extern const struct clk_ops mtk_clk_topckgen_ops;
 extern const struct clk_ops mtk_clk_infrasys_ops;
 extern const struct clk_ops mtk_clk_gate_ops;
 
+int mtk_common_clk_parent_bind(struct udevice *dev);
 int mtk_common_clk_init(struct udevice *dev,
 			const struct mtk_clk_tree *tree);
-int mtk_common_clk_infrasys_init(struct udevice *dev,
-				 const struct mtk_clk_tree *tree);
 int mtk_common_clk_gate_init(struct udevice *dev,
 			     const struct mtk_clk_tree *tree,
 			     const struct mtk_gate *gates, int num_gates,
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index bb9c52155d2..12b0e2c9914 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -9,6 +9,14 @@ config POWER_DOMAIN
 	  domains). This may be used to save power. This API provides the
 	  means to control such power management hardware.
 
+config AGILEX5_PMGR_POWER_DOMAIN
+	bool "Enable the Agilex5 PMGR power domain driver"
+	depends on SPL_POWER_DOMAIN && ARCH_SOCFPGA_SOC64
+	help
+	  Enable support for power gating peripherals' SRAM specified in
+	  the handoff data values obtained from the bitstream to reduce
+	  power consumption.
+
 config APPLE_PMGR_POWER_DOMAIN
 	bool "Enable the Apple PMGR power domain driver"
 	depends on POWER_DOMAIN
@@ -18,14 +26,6 @@ config APPLE_PMGR_POWER_DOMAIN
 	  This driver is needed to power on parts of the SoC that have
 	  not been powered on by previous boot stages.
 
-config AGILEX5_PMGR_POWER_DOMAIN
-	bool "Enable the Agilex5 PMGR power domain driver"
-	depends on SPL_POWER_DOMAIN && ARCH_SOCFPGA_SOC64
-	help
-	  Enable support for power gating peripherals' SRAM specified in
-	  the handoff data values obtained from the bitstream to reduce
-	  power consumption.
-
 config BCM6328_POWER_DOMAIN
 	bool "Enable the BCM6328 power domain driver"
 	depends on POWER_DOMAIN && ARCH_BMIPS
@@ -62,12 +62,12 @@ config IMX8MP_MEDIAMIX_BLKCTRL
 	help
 	  Enable support for manipulating NXP i.MX8MP on-SoC MEDIAMIX block controller.
 
-config MTK_POWER_DOMAIN
-	bool "Enable the MediaTek power domain driver"
-	depends on POWER_DOMAIN && ARCH_MEDIATEK
+config MESON_EE_POWER_DOMAIN
+	bool "Enable Amlogic Everything-Else power domain driver"
+	depends on POWER_DOMAIN && ARCH_MESON
 	help
-	  Enable support for manipulating MediaTek power domains via MMIO
-	  mapped registers.
+	  Enable support for manipulating Amlogic Meson Everything-Else power
+	  domains.
 
 config MESON_GX_VPU_POWER_DOMAIN
 	bool "Enable Amlogic Meson GX VPU power domain driver"
@@ -76,13 +76,6 @@ config MESON_GX_VPU_POWER_DOMAIN
 	  Enable support for manipulating Amlogic Meson GX Video Processing
 	  Unit power domain.
 
-config MESON_EE_POWER_DOMAIN
-	bool "Enable Amlogic Everything-Else power domain driver"
-	depends on POWER_DOMAIN && ARCH_MESON
-	help
-	  Enable support for manipulating Amlogic Meson Everything-Else power
-	  domains.
-
 config MESON_SECURE_POWER_DOMAIN
 	bool "Enable Amlogic Secure power domain driver"
 	depends on POWER_DOMAIN && ARCH_MESON && MESON_A1
@@ -90,6 +83,40 @@ config MESON_SECURE_POWER_DOMAIN
 	  Enable support for manipulating Amlogic Meson Secure power domains.
 	  Support for Amlogic A1 series.
 
+config MT2701_POWER_DOMAIN
+	bool "Enable the MediaTek power domain driver for MT2701 compatible SoC"
+	depends on POWER_DOMAIN && ARCH_MEDIATEK
+	select MTK_POWER_DOMAIN
+	help
+	  Enable support for manipulating MediaTek power domains via MMIO
+	  mapped registers for MT2701 compatible SoC. The driver powers
+	  the SoC power domains on and off and handles the associated bus
+	  protection bits. It is also used on MT7623.
+
+config MT7622_POWER_DOMAIN
+	bool "Enable the MediaTek power domain driver for MT7622 compatible SoC"
+	depends on POWER_DOMAIN && ARCH_MEDIATEK
+	select MTK_POWER_DOMAIN
+	help
+	  Enable support for manipulating MediaTek power domains via MMIO
+	  mapped registers for MT7622 compatible SoC. The driver powers
+	  the SoC power domains on and off and handles the associated bus
+	  protection bits. It is also used on MT7629.
+
+config MT8188_POWER_DOMAIN
+	bool "Enable the MediaTek power domain driver for MT8188 compatible SoC"
+	depends on POWER_DOMAIN && ARCH_MEDIATEK
+	select MTK_POWER_DOMAIN
+	help
+	  Enable support for manipulating MediaTek power domains via MMIO
+	  mapped registers for MT8188 compatible SoC. The driver powers
+	  the SoC power domains on and off and handles the associated bus
+	  protection steps, per-domain clocks and parent domains.
+
+config MTK_POWER_DOMAIN
+	bool
+	depends on POWER_DOMAIN && ARCH_MEDIATEK
+
 config QCOM_RPMH_POWER_DOMAIN
 	bool "Enable the QCOM RPMH Power domain driver"
 	depends on POWER_DOMAIN && ARCH_SNAPDRAGON
@@ -128,12 +155,13 @@ config TEGRA186_POWER_DOMAIN
 	  Enable support for manipulating Tegra's on-SoC power domains via IPC
 	  requests to the BPMP (Boot and Power Management Processor).
 
-config TI_SCI_POWER_DOMAIN
-	bool "Enable the TI SCI-based power domain driver"
-	depends on POWER_DOMAIN && TI_SCI_PROTOCOL
+config TI_OMAP_PRM_POWER_DOMAIN
+	bool "Enable the TI OMAP PRM power domain driver"
+	depends on POWER_DOMAIN && ARCH_OMAP2PLUS
 	help
-	  Generic power domain implementation for TI devices implementing the
-	  TI SCI protocol.
+	  Enable support for TI OMAP Power and Reset Manager (PRM) power domains.
+	  The driver is currently a stub to be able to probe devices that
+	  require this type of power domain device.
 
 config TI_POWER_DOMAIN
 	bool "Enable the TI K3 Power domain driver"
@@ -141,13 +169,12 @@ config TI_POWER_DOMAIN
 	help
 	  Generic power domain implementation for TI K3 devices.
 
-config TI_OMAP_PRM_POWER_DOMAIN
-	bool "Enable the TI OMAP PRM power domain driver"
-	depends on POWER_DOMAIN && ARCH_OMAP2PLUS
+config TI_SCI_POWER_DOMAIN
+	bool "Enable the TI SCI-based power domain driver"
+	depends on POWER_DOMAIN && TI_SCI_PROTOCOL
 	help
-	  Enable support for TI OMAP Power and Reset Manager (PRM) power domains.
-	  The driver is currently a stub to be able to probe devices that
-	  require this type of power domain device.
+	  Generic power domain implementation for TI devices implementing the
+	  TI SCI protocol.
 
 config ZYNQMP_POWER_DOMAIN
 	bool "Enable the Xilinx ZynqMP Power domain driver"
diff --git a/drivers/power/domain/Makefile b/drivers/power/domain/Makefile
index 110153d5cf8..e6fe71c374a 100644
--- a/drivers/power/domain/Makefile
+++ b/drivers/power/domain/Makefile
@@ -4,24 +4,27 @@
 #
 
 obj-$(CONFIG_$(PHASE_)POWER_DOMAIN) += power-domain-uclass.o
-obj-$(CONFIG_APPLE_PMGR_POWER_DOMAIN) += apple-pmgr.o
 obj-$(CONFIG_AGILEX5_PMGR_POWER_DOMAIN) += altr-pmgr-agilex5.o
+obj-$(CONFIG_APPLE_PMGR_POWER_DOMAIN) += apple-pmgr.o
 obj-$(CONFIG_BCM6328_POWER_DOMAIN) += bcm6328-power-domain.o
 obj-$(CONFIG_IMX8_POWER_DOMAIN) += imx8-power-domain-legacy.o imx8-power-domain.o
 obj-$(CONFIG_IMX8M_POWER_DOMAIN) += imx8m-power-domain.o
 obj-$(CONFIG_IMX8MP_HSIOMIX_BLKCTRL) += imx8mp-hsiomix.o
 obj-$(CONFIG_IMX8MP_MEDIAMIX_BLKCTRL) += imx8mp-mediamix.o
-obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o
-obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o
 obj-$(CONFIG_MESON_EE_POWER_DOMAIN) += meson-ee-pwrc.o
+obj-$(CONFIG_MESON_GX_VPU_POWER_DOMAIN) += meson-gx-pwrc-vpu.o
 obj-$(CONFIG_MESON_SECURE_POWER_DOMAIN) += meson-secure-pwrc.o
+obj-$(CONFIG_MT2701_POWER_DOMAIN) += mt2701-power-domain.o
+obj-$(CONFIG_MT7622_POWER_DOMAIN) += mt7622-power-domain.o
+obj-$(CONFIG_MT8188_POWER_DOMAIN) += mt8188-power-domain.o
+obj-$(CONFIG_MTK_POWER_DOMAIN) += mtk-power-domain.o
+obj-$(CONFIG_QCOM_RPMH_POWER_DOMAIN) += qcom-rpmhpd.o
 obj-$(CONFIG_RENESAS_R8A78000_POWER_DOMAIN) += renesas-r8a78000-power-domain.o
 obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain.o
 obj-$(CONFIG_SANDBOX_POWER_DOMAIN) += sandbox-power-domain-test.o
 obj-$(CONFIG_SCMI_POWER_DOMAIN) += scmi-power-domain.o
 obj-$(CONFIG_TEGRA186_POWER_DOMAIN) += tegra186-power-domain.o
-obj-$(CONFIG_TI_SCI_POWER_DOMAIN) += ti-sci-power-domain.o
-obj-$(CONFIG_TI_POWER_DOMAIN) += ti-power-domain.o
 obj-$(CONFIG_TI_OMAP_PRM_POWER_DOMAIN) += ti-omap-prm.o
+obj-$(CONFIG_TI_POWER_DOMAIN) += ti-power-domain.o
+obj-$(CONFIG_TI_SCI_POWER_DOMAIN) += ti-sci-power-domain.o
 obj-$(CONFIG_ZYNQMP_POWER_DOMAIN) += zynqmp-power-domain.o
-obj-$(CONFIG_QCOM_RPMH_POWER_DOMAIN) += qcom-rpmhpd.o
diff --git a/drivers/power/domain/mt2701-power-domain.c b/drivers/power/domain/mt2701-power-domain.c
new file mode 100644
index 00000000000..5bef4aa97ea
--- /dev/null
+++ b/drivers/power/domain/mt2701-power-domain.c
@@ -0,0 +1,89 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Copyright (C) 2026 BayLibre, SAS
+ * Author: Ryder Lee <[email protected]>
+ *         Julien Stephan <[email protected]>
+ */
+
+#include <dm.h>
+#include <dt-bindings/power/mt2701-power.h>
+#include <linux/bitops.h>
+
+#include "mtk-power-domain.h"
+
+static const struct mtk_scp_domain_data mt2701_scp_domain[] = {
+	[MT2701_POWER_DOMAIN_CONN] = {
+		.sta_mask = PWR_STATUS_CONN,
+		.ctl_offs = SPM_CONN_PWR_CON,
+		.bus_prot_mask = BIT(8) | BIT(2),
+	},
+	[MT2701_POWER_DOMAIN_DISP] = {
+		.sta_mask = PWR_STATUS_DISP,
+		.ctl_offs = SPM_DIS_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.bus_prot_mask = BIT(2),
+	},
+	[MT2701_POWER_DOMAIN_MFG] = {
+		.sta_mask = PWR_STATUS_MFG,
+		.ctl_offs = SPM_MFG_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(12, 12),
+	},
+	[MT2701_POWER_DOMAIN_VDEC] = {
+		.sta_mask = PWR_STATUS_VDEC,
+		.ctl_offs = SPM_VDE_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(12, 12),
+	},
+	[MT2701_POWER_DOMAIN_ISP] = {
+		.sta_mask = PWR_STATUS_ISP,
+		.ctl_offs = SPM_ISP_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(13, 12),
+	},
+	[MT2701_POWER_DOMAIN_BDP] = {
+		.sta_mask = PWR_STATUS_BDP,
+		.ctl_offs = SPM_BDP_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+	},
+	[MT2701_POWER_DOMAIN_ETH] = {
+		.sta_mask = PWR_STATUS_ETH,
+		.ctl_offs = SPM_ETH_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(15, 12),
+	},
+	[MT2701_POWER_DOMAIN_HIF] = {
+		.sta_mask = PWR_STATUS_HIF,
+		.ctl_offs = SPM_HIF_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(15, 12),
+	},
+	[MT2701_POWER_DOMAIN_IFR_MSC] = {
+		.sta_mask = PWR_STATUS_IFR_MSC,
+		.ctl_offs = SPM_IFR_MSC_PWR_CON,
+	},
+};
+
+MTK_SCP_SOC_DATA(mt2701, mt2701_scp_domain);
+
+static const struct udevice_id mt2701_power_domain_ids[] = {
+	{
+		.compatible = "mediatek,mt2701-scpsys",
+		.data = (ulong)&mt2701_scp_soc_data,
+	},
+	{
+		.compatible = "mediatek,mt7623-scpsys",
+		.data = (ulong)&mt2701_scp_soc_data,
+	},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mt2701_power_domain) = {
+	.name = "mt2701_power_domain",
+	.id = UCLASS_POWER_DOMAIN,
+	.ops = &mtk_power_domain_ops,
+	.probe = mtk_scpsys_probe,
+	.of_match = mt2701_power_domain_ids,
+	.priv_auto = sizeof(struct mtk_scpsys),
+};
diff --git a/drivers/power/domain/mt7622-power-domain.c b/drivers/power/domain/mt7622-power-domain.c
new file mode 100644
index 00000000000..13f2154e145
--- /dev/null
+++ b/drivers/power/domain/mt7622-power-domain.c
@@ -0,0 +1,56 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Copyright (C) 2026 BayLibre, SAS
+ * Author: Ryder Lee <[email protected]>
+ *         Julien Stephan <[email protected]>
+ */
+
+#include <dm.h>
+#include <dt-bindings/power/mt7622-power.h>
+#include <linux/bitops.h>
+
+#include "mtk-power-domain.h"
+
+static const struct mtk_scp_domain_data mt7622_scp_domain[] = {
+	[MT7622_POWER_DOMAIN_ETHSYS] = {
+		.sta_mask = PWR_STATUS_ETHSYS,
+		.ctl_offs = SPM_ETHSYS_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(15, 12),
+		.bus_prot_mask = (BIT(3) | BIT(17)),
+	},
+	[MT7622_POWER_DOMAIN_HIF0] = {
+		.sta_mask = PWR_STATUS_HIF0,
+		.ctl_offs = SPM_HIF0_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(15, 12),
+		.bus_prot_mask = GENMASK(25, 24),
+	},
+	[MT7622_POWER_DOMAIN_HIF1] = {
+		.sta_mask = PWR_STATUS_HIF1,
+		.ctl_offs = SPM_HIF1_PWR_CON,
+		.sram_pdn_bits = GENMASK(11, 8),
+		.sram_pdn_ack_bits = GENMASK(15, 12),
+		.bus_prot_mask = GENMASK(28, 26),
+	},
+};
+
+MTK_SCP_SOC_DATA(mt7622, mt7622_scp_domain);
+
+static const struct udevice_id mt7622_power_domain_ids[] = {
+	{
+		.compatible = "mediatek,mt7622-scpsys",
+		.data = (ulong)&mt7622_scp_soc_data,
+	},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mt7622_power_domain) = {
+	.name = "mt7622_power_domain",
+	.id = UCLASS_POWER_DOMAIN,
+	.ops = &mtk_power_domain_ops,
+	.probe = mtk_scpsys_probe,
+	.of_match = mt7622_power_domain_ids,
+	.priv_auto = sizeof(struct mtk_scpsys),
+};
diff --git a/drivers/power/domain/mt8188-power-domain.c b/drivers/power/domain/mt8188-power-domain.c
new file mode 100644
index 00000000000..265d222f17a
--- /dev/null
+++ b/drivers/power/domain/mt8188-power-domain.c
@@ -0,0 +1,665 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2026 MediaTek Inc.
+ * Copyright (C) 2026 BayLibre, SAS.
+ * Authors: Chris-QJ Chen <[email protected]>
+ *          Julien Stephan <[email protected]>
+ */
+
+#include <dm.h>
+#include <dt-bindings/power/mediatek,mt8188-power.h>
+#include <linux/bitops.h>
+
+#include "mtk-power-domain.h"
+
+/* Infra bus protection register offsets */
+#define MT8188_TOP_AXI_PROT_EN_SET			0x2A0
+#define MT8188_TOP_AXI_PROT_EN_CLR			0x2A4
+#define MT8188_TOP_AXI_PROT_EN_STA			0x228
+#define MT8188_TOP_AXI_PROT_EN_1_SET			0x2A8
+#define MT8188_TOP_AXI_PROT_EN_1_CLR			0x2AC
+#define MT8188_TOP_AXI_PROT_EN_1_STA			0x258
+#define MT8188_TOP_AXI_PROT_EN_2_SET			0x714
+#define MT8188_TOP_AXI_PROT_EN_2_CLR			0x718
+#define MT8188_TOP_AXI_PROT_EN_2_STA			0x724
+#define MT8188_TOP_AXI_PROT_EN_MM_SET			0x2D4
+#define MT8188_TOP_AXI_PROT_EN_MM_CLR			0x2D8
+#define MT8188_TOP_AXI_PROT_EN_MM_STA			0x2EC
+#define MT8188_TOP_AXI_PROT_EN_MM_2_SET			0xDCC
+#define MT8188_TOP_AXI_PROT_EN_MM_2_CLR			0xDD0
+#define MT8188_TOP_AXI_PROT_EN_MM_2_STA			0xDD8
+#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET		0xB84
+#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR		0xB88
+#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA		0xB90
+#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET	0xBCC
+#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR	0xBD0
+#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA	0xBD8
+
+/* MFG1 bus protection bits */
+#define MT8188_TOP_AXI_PROT_EN_MFG1_STEP1			BIT(11)
+#define MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2			BIT(7)
+#define MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3			BIT(19)
+#define MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4			BIT(5)
+#define MT8188_TOP_AXI_PROT_EN_MFG1_STEP5			GENMASK(22, 21)
+#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6	BIT(17)
+
+/* PCIe bus protection bits */
+#define MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1		BIT(2)
+#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2	(BIT(8) | BIT(18) | BIT(30))
+
+/* Ethernet / HDMI / DP / eDP bus protection bits */
+#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1		BIT(24)
+#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1		BIT(20)
+#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1		BIT(23)
+#define MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1		BIT(22)
+
+/* ADSP bus protection bits */
+#define MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1			GENMASK(31, 29)
+#define MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2			(GENMASK(4, 3) | BIT(28))
+#define MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1		(GENMASK(16, 14) | BIT(23) | BIT(27))
+#define MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2		(GENMASK(19, 17) | GENMASK(26, 25))
+#define MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1			GENMASK(11, 8)
+#define MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2			GENMASK(22, 21)
+
+/* Audio bus protection bits */
+#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1			BIT(20)
+#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2			BIT(12)
+#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1		BIT(24)
+#define MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2		BIT(13)
+
+/* Video / display bus protection bits */
+#define MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1			BIT(10)
+#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2		GENMASK(9, 8)
+#define MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3			BIT(23)
+#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4		(BIT(1) | BIT(4) | BIT(11))
+#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5	BIT(20)
+#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1			(GENMASK(18, 17) | GENMASK(21, 20))
+#define MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2			BIT(6)
+#define MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3	BIT(21)
+#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1			GENMASK(31, 30)
+#define MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2			BIT(22)
+#define MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3		BIT(10)
+#define MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1			GENMASK(6, 5)
+#define MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2			BIT(23)
+#define MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3		BIT(18)
+#define MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1			BIT(23)
+#define MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2			BIT(21)
+#define MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1			BIT(13)
+#define MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2			BIT(13)
+#define MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1			BIT(14)
+#define MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2			BIT(29)
+#define MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1			(BIT(9) | BIT(11))
+#define MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2			BIT(26)
+#define MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3			BIT(2)
+#define MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1		(BIT(1) | BIT(3))
+#define MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2		BIT(25)
+#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3		BIT(16)
+#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1		GENMASK(27, 26)
+#define MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2		GENMASK(25, 24)
+#define MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1		(BIT(2) | BIT(4))
+#define MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2		BIT(0)
+#define MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3		BIT(22)
+#define MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4		BIT(24)
+#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5		BIT(17)
+#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1		GENMASK(31, 30)
+#define MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2			BIT(2)
+#define MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3		GENMASK(29, 28)
+#define MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4			BIT(1)
+
+static const struct mtk_scp_domain_data mt8188_scp_domain[] = {
+	[MT8188_POWER_DOMAIN_MFG0] = {
+		.sta_mask = BIT(1),
+		.ctl_offs = 0x300,
+		.pwr_sta_offs = 0x174,
+		.pwr_sta2nd_offs = 0x178,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+	},
+	[MT8188_POWER_DOMAIN_MFG1] = {
+		.sta_mask = BIT(2),
+		.ctl_offs = 0x304,
+		.pwr_sta_offs = 0x174,
+		.pwr_sta2nd_offs = 0x178,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_SET,
+				    MT8188_TOP_AXI_PROT_EN_CLR,
+				    MT8188_TOP_AXI_PROT_EN_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP2,
+				    MT8188_TOP_AXI_PROT_EN_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_2_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_MFG1_STEP3,
+				    MT8188_TOP_AXI_PROT_EN_1_SET,
+				    MT8188_TOP_AXI_PROT_EN_1_CLR,
+				    MT8188_TOP_AXI_PROT_EN_1_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_MFG1_STEP4,
+				    MT8188_TOP_AXI_PROT_EN_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_2_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MFG1_STEP5,
+				    MT8188_TOP_AXI_PROT_EN_SET,
+				    MT8188_TOP_AXI_PROT_EN_CLR,
+				    MT8188_TOP_AXI_PROT_EN_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_MFG1_STEP6,
+				    MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
+				    MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
+				    MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_MFG2] = {
+		.sta_mask = BIT(3),
+		.ctl_offs = 0x308,
+		.pwr_sta_offs = 0x174,
+		.pwr_sta2nd_offs = 0x178,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+	},
+	[MT8188_POWER_DOMAIN_MFG3] = {
+		.sta_mask = BIT(4),
+		.ctl_offs = 0x30C,
+		.pwr_sta_offs = 0x174,
+		.pwr_sta2nd_offs = 0x178,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+	},
+	[MT8188_POWER_DOMAIN_MFG4] = {
+		.sta_mask = BIT(5),
+		.ctl_offs = 0x310,
+		.pwr_sta_offs = 0x174,
+		.pwr_sta2nd_offs = 0x178,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+	},
+	[MT8188_POWER_DOMAIN_PEXTP_MAC_P0] = {
+		.sta_mask = BIT(10),
+		.ctl_offs = 0x324,
+		.pwr_sta_offs = 0x174,
+		.pwr_sta2nd_offs = 0x178,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_PEXTP_MAC_P0_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_SET,
+				    MT8188_TOP_AXI_PROT_EN_CLR,
+				    MT8188_TOP_AXI_PROT_EN_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_PEXTP_MAC_P0_STEP2,
+				    MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
+				    MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
+				    MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_PEXTP_PHY_TOP] = {
+		.sta_mask = BIT(12),
+		.ctl_offs = 0x328,
+		.pwr_sta_offs = 0x174,
+		.pwr_sta2nd_offs = 0x178,
+	},
+	[MT8188_POWER_DOMAIN_CSIRX_TOP] = {
+		.sta_mask = BIT(17),
+		.ctl_offs = 0x3C4,
+		.pwr_sta_offs = 0x174,
+		.pwr_sta2nd_offs = 0x178,
+	},
+	[MT8188_POWER_DOMAIN_ETHER] = {
+		.sta_mask = BIT(1),
+		.ctl_offs = 0x338,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_ETHER_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
+				    MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
+				    MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_HDMI_TX] = {
+		.sta_mask = BIT(18),
+		.ctl_offs = 0x37C,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_HDMI_TX_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
+				    MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
+				    MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_ADSP_AO] = {
+		.sta_mask = BIT(10),
+		.ctl_offs = 0x35C,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_2_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_AO_STEP2,
+				    MT8188_TOP_AXI_PROT_EN_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_2_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_ADSP_INFRA] = {
+		.sta_mask = BIT(9),
+		.ctl_offs = 0x358,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_2_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_INFRA_STEP2,
+				    MT8188_TOP_AXI_PROT_EN_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_2_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_ADSP] = {
+		.sta_mask = BIT(8),
+		.ctl_offs = 0x354,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_2_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_ADSP_STEP2,
+				    MT8188_TOP_AXI_PROT_EN_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_2_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_AUDIO] = {
+		.sta_mask = BIT(6),
+		.ctl_offs = 0x34C,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_2_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_STEP2,
+				    MT8188_TOP_AXI_PROT_EN_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_2_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_AUDIO_ASRC] = {
+		.sta_mask = BIT(7),
+		.ctl_offs = 0x350,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_2_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_AUDIO_ASRC_STEP2,
+				    MT8188_TOP_AXI_PROT_EN_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_2_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_VPPSYS0] = {
+		.sta_mask = BIT(11),
+		.ctl_offs = 0x360,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_SET,
+				    MT8188_TOP_AXI_PROT_EN_CLR,
+				    MT8188_TOP_AXI_PROT_EN_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP2,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VPPSYS0_STEP3,
+				    MT8188_TOP_AXI_PROT_EN_SET,
+				    MT8188_TOP_AXI_PROT_EN_CLR,
+				    MT8188_TOP_AXI_PROT_EN_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS0_STEP4,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VPPSYS0_STEP5,
+				    MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
+				    MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
+				    MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_VDOSYS0] = {
+		.sta_mask = BIT(13),
+		.ctl_offs = 0x368,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS0_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_MM_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_VDOSYS0_STEP2,
+				    MT8188_TOP_AXI_PROT_EN_SET,
+				    MT8188_TOP_AXI_PROT_EN_CLR,
+				    MT8188_TOP_AXI_PROT_EN_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_VDOSYS0_STEP3,
+				    MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_SET,
+				    MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_CLR,
+				    MT8188_TOP_AXI_PROT_EN_SUB_INFRA_VDNR_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_VDOSYS1] = {
+		.sta_mask = BIT(14),
+		.ctl_offs = 0x36C,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_MM_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDOSYS1_STEP2,
+				    MT8188_TOP_AXI_PROT_EN_MM_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDOSYS1_STEP3,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_DP_TX] = {
+		.sta_mask = BIT(16),
+		.ctl_offs = 0x374,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_DP_TX_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
+				    MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
+				    MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_EDP_TX] = {
+		.sta_mask = BIT(17),
+		.ctl_offs = 0x378,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_EDP_TX_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_SET,
+				    MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_CLR,
+				    MT8188_TOP_AXI_PROT_EN_INFRA_VDNR_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_VPPSYS1] = {
+		.sta_mask = BIT(12),
+		.ctl_offs = 0x364,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_MM_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VPPSYS1_STEP2,
+				    MT8188_TOP_AXI_PROT_EN_MM_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VPPSYS1_STEP3,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_WPE] = {
+		.sta_mask = BIT(15),
+		.ctl_offs = 0x370,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_WPE_STEP2,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_VDEC0] = {
+		.sta_mask = BIT(19),
+		.ctl_offs = 0x380,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC0_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_MM_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VDEC0_STEP2,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_VDEC1] = {
+		.sta_mask = BIT(20),
+		.ctl_offs = 0x384,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_MM_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VDEC1_STEP2,
+				    MT8188_TOP_AXI_PROT_EN_MM_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_VENC] = {
+		.sta_mask = BIT(22),
+		.ctl_offs = 0x38C,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_MM_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_VENC_STEP2,
+				    MT8188_TOP_AXI_PROT_EN_MM_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_VENC_STEP3,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_IMG_VCORE] = {
+		.sta_mask = BIT(28),
+		.ctl_offs = 0x3A4,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_MM_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_IMG_VCORE_STEP2,
+				    MT8188_TOP_AXI_PROT_EN_MM_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_VCORE_STEP3,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_IMG_MAIN] = {
+		.sta_mask = BIT(29),
+		.ctl_offs = 0x3A8,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_IMG_MAIN_STEP2,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_DIP] = {
+		.sta_mask = BIT(30),
+		.ctl_offs = 0x3AC,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+	},
+	[MT8188_POWER_DOMAIN_IPE] = {
+		.sta_mask = BIT(31),
+		.ctl_offs = 0x3B0,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+	},
+	[MT8188_POWER_DOMAIN_CAM_VCORE] = {
+		.sta_mask = BIT(27),
+		.ctl_offs = 0x3A0,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_MM_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_VCORE_STEP2,
+				    MT8188_TOP_AXI_PROT_EN_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_2_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_1_CAM_VCORE_STEP3,
+				    MT8188_TOP_AXI_PROT_EN_1_SET,
+				    MT8188_TOP_AXI_PROT_EN_1_CLR,
+				    MT8188_TOP_AXI_PROT_EN_1_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_CAM_VCORE_STEP4,
+				    MT8188_TOP_AXI_PROT_EN_MM_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_VCORE_STEP5,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_CAM_MAIN] = {
+		.sta_mask = BIT(24),
+		.ctl_offs = 0x394,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+		.bp_infracfg = {
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP1,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP2,
+				    MT8188_TOP_AXI_PROT_EN_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_2_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_MM_2_CAM_MAIN_STEP3,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_MM_2_STA),
+			BUS_PROT_WR(MT8188_TOP_AXI_PROT_EN_2_CAM_MAIN_STEP4,
+				    MT8188_TOP_AXI_PROT_EN_2_SET,
+				    MT8188_TOP_AXI_PROT_EN_2_CLR,
+				    MT8188_TOP_AXI_PROT_EN_2_STA),
+		},
+	},
+	[MT8188_POWER_DOMAIN_CAM_SUBA] = {
+		.sta_mask = BIT(25),
+		.ctl_offs = 0x398,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+	},
+	[MT8188_POWER_DOMAIN_CAM_SUBB] = {
+		.sta_mask = BIT(26),
+		.ctl_offs = 0x39C,
+		.pwr_sta_offs = 0x16C,
+		.pwr_sta2nd_offs = 0x170,
+		.sram_pdn_bits = BIT(8),
+		.sram_pdn_ack_bits = BIT(12),
+	},
+};
+
+MTK_SCP_SOC_DATA(mt8188, mt8188_scp_domain);
+
+static const struct udevice_id mt8188_power_domain_ids[] = {
+	{
+		.compatible = "mediatek,mt8188-power-controller",
+		.data = (ulong)&mt8188_scp_soc_data,
+	},
+	{ /* sentinel */ }
+};
+
+U_BOOT_DRIVER(mt8188_power_domain) = {
+	.name = "mt8188_power_domain",
+	.id = UCLASS_POWER_DOMAIN,
+	.ops = &mtk_power_domain_ops,
+	.probe = mtk_power_controller_probe,
+	.of_match = mt8188_power_domain_ids,
+	.priv_auto = sizeof(struct mtk_scpsys),
+};
diff --git a/drivers/power/domain/mtk-power-domain.c b/drivers/power/domain/mtk-power-domain.c
index 24dd540897d..9eef58d2d57 100644
--- a/drivers/power/domain/mtk-power-domain.c
+++ b/drivers/power/domain/mtk-power-domain.c
@@ -6,161 +6,15 @@
 
 #include <clk.h>
 #include <dm.h>
-#include <malloc.h>
-#include <power-domain-uclass.h>
 #include <regmap.h>
 #include <syscon.h>
 #include <asm/io.h>
-#include <asm/processor.h>
-#include <linux/bitops.h>
 #include <linux/err.h>
 #include <linux/iopoll.h>
+#include <dm/device_compat.h>
+#include <dm/devres.h>
 
-#include <dt-bindings/power/mt7623-power.h>
-#include <dt-bindings/power/mt7629-power.h>
-
-#define SPM_EN			(0xb16 << 16 | 0x1)
-#define SPM_VDE_PWR_CON		0x0210
-#define SPM_MFG_PWR_CON		0x0214
-#define SPM_ISP_PWR_CON		0x0238
-#define SPM_DIS_PWR_CON		0x023c
-#define SPM_CONN_PWR_CON	0x0280
-#define SPM_BDP_PWR_CON		0x029c
-#define SPM_ETH_PWR_CON		0x02a0
-#define SPM_HIF_PWR_CON		0x02a4
-#define SPM_IFR_MSC_PWR_CON	0x02a8
-#define SPM_ETHSYS_PWR_CON	0x2e0
-#define SPM_HIF0_PWR_CON	0x2e4
-#define SPM_HIF1_PWR_CON	0x2e8
-#define SPM_PWR_STATUS		0x60c
-#define SPM_PWR_STATUS_2ND	0x610
-
-#define PWR_RST_B_BIT		BIT(0)
-#define PWR_ISO_BIT		BIT(1)
-#define PWR_ON_BIT		BIT(2)
-#define PWR_ON_2ND_BIT		BIT(3)
-#define PWR_CLK_DIS_BIT		BIT(4)
-
-#define PWR_STATUS_CONN		BIT(1)
-#define PWR_STATUS_DISP		BIT(3)
-#define PWR_STATUS_MFG		BIT(4)
-#define PWR_STATUS_ISP		BIT(5)
-#define PWR_STATUS_VDEC		BIT(7)
-#define PWR_STATUS_BDP		BIT(14)
-#define PWR_STATUS_ETH		BIT(15)
-#define PWR_STATUS_HIF		BIT(16)
-#define PWR_STATUS_IFR_MSC	BIT(17)
-#define PWR_STATUS_ETHSYS	BIT(24)
-#define PWR_STATUS_HIF0		BIT(25)
-#define PWR_STATUS_HIF1		BIT(26)
-
-/* Infrasys configuration */
-#define INFRA_TOPDCM_CTRL	0x10
-#define INFRA_TOPAXI_PROT_EN	0x220
-#define INFRA_TOPAXI_PROT_STA1	0x228
-
-#define DCM_TOP_EN		BIT(0)
-
-enum scp_domain_type {
-	SCPSYS_MT7622,
-	SCPSYS_MT7623,
-	SCPSYS_MT7629,
-};
-
-struct scp_domain;
-
-struct scp_domain_data {
-	struct scp_domain *scpd;
-	u32 sta_mask;
-	int ctl_offs;
-	u32 sram_pdn_bits;
-	u32 sram_pdn_ack_bits;
-	u32 bus_prot_mask;
-};
-
-struct scp_domain {
-	void __iomem *base;
-	void __iomem *infracfg;
-	enum scp_domain_type type;
-	struct scp_domain_data *data;
-};
-
-static struct scp_domain_data scp_domain_mt7623[] = {
-	[MT7623_POWER_DOMAIN_CONN] = {
-		.sta_mask = PWR_STATUS_CONN,
-		.ctl_offs = SPM_CONN_PWR_CON,
-		.bus_prot_mask = BIT(8) | BIT(2),
-	},
-	[MT7623_POWER_DOMAIN_DISP] = {
-		.sta_mask = PWR_STATUS_DISP,
-		.ctl_offs = SPM_DIS_PWR_CON,
-		.sram_pdn_bits = GENMASK(11, 8),
-		.bus_prot_mask = BIT(2),
-	},
-	[MT7623_POWER_DOMAIN_MFG] = {
-		.sta_mask = PWR_STATUS_MFG,
-		.ctl_offs = SPM_MFG_PWR_CON,
-		.sram_pdn_bits = GENMASK(11, 8),
-		.sram_pdn_ack_bits = GENMASK(12, 12),
-	},
-	[MT7623_POWER_DOMAIN_VDEC] = {
-		.sta_mask = PWR_STATUS_VDEC,
-		.ctl_offs = SPM_VDE_PWR_CON,
-		.sram_pdn_bits = GENMASK(11, 8),
-		.sram_pdn_ack_bits = GENMASK(12, 12),
-	},
-	[MT7623_POWER_DOMAIN_ISP] = {
-		.sta_mask = PWR_STATUS_ISP,
-		.ctl_offs = SPM_ISP_PWR_CON,
-		.sram_pdn_bits = GENMASK(11, 8),
-		.sram_pdn_ack_bits = GENMASK(13, 12),
-	},
-	[MT7623_POWER_DOMAIN_BDP] = {
-		.sta_mask = PWR_STATUS_BDP,
-		.ctl_offs = SPM_BDP_PWR_CON,
-		.sram_pdn_bits = GENMASK(11, 8),
-	},
-	[MT7623_POWER_DOMAIN_ETH] = {
-		.sta_mask = PWR_STATUS_ETH,
-		.ctl_offs = SPM_ETH_PWR_CON,
-		.sram_pdn_bits = GENMASK(11, 8),
-		.sram_pdn_ack_bits = GENMASK(15, 12),
-	},
-	[MT7623_POWER_DOMAIN_HIF] = {
-		.sta_mask = PWR_STATUS_HIF,
-		.ctl_offs = SPM_HIF_PWR_CON,
-		.sram_pdn_bits = GENMASK(11, 8),
-		.sram_pdn_ack_bits = GENMASK(15, 12),
-	},
-	[MT7623_POWER_DOMAIN_IFR_MSC] = {
-		.sta_mask = PWR_STATUS_IFR_MSC,
-		.ctl_offs = SPM_IFR_MSC_PWR_CON,
-	},
-};
-
-static struct scp_domain_data scp_domain_mt7629[] = {
-	[MT7629_POWER_DOMAIN_ETHSYS] = {
-		.sta_mask = PWR_STATUS_ETHSYS,
-		.ctl_offs = SPM_ETHSYS_PWR_CON,
-		.sram_pdn_bits = GENMASK(11, 8),
-		.sram_pdn_ack_bits = GENMASK(15, 12),
-		.bus_prot_mask = (BIT(3) | BIT(17)),
-	},
-	[MT7629_POWER_DOMAIN_HIF0] = {
-		.sta_mask = PWR_STATUS_HIF0,
-		.ctl_offs = SPM_HIF0_PWR_CON,
-		.sram_pdn_bits = GENMASK(11, 8),
-		.sram_pdn_ack_bits = GENMASK(15, 12),
-		.bus_prot_mask = GENMASK(25, 24),
-	},
-	[MT7629_POWER_DOMAIN_HIF1] = {
-		.sta_mask = PWR_STATUS_HIF1,
-		.ctl_offs = SPM_HIF1_PWR_CON,
-		.sram_pdn_bits = GENMASK(11, 8),
-		.sram_pdn_ack_bits = GENMASK(15, 12),
-		.bus_prot_mask = GENMASK(28, 26),
-	},
-};
+#include "mtk-power-domain.h"
 
 /**
  * This function enables the bus protection bits for disabled power
@@ -189,13 +43,79 @@ static int mtk_infracfg_clear_bus_protection(void __iomem *infracfg,
 				  !(val & mask), 100);
 }
 
-static int scpsys_domain_is_on(struct scp_domain_data *data)
+static int _scpsys_bus_protect_enable(const struct mtk_scpsys_bus_prot_data *bpd,
+				      void __iomem *reg)
+{
+	u32 val = 0, mask = bpd->bus_prot_mask;
+
+	if (!mask)
+		return 0;
+
+	if (bpd->bus_prot_reg_update)
+		clrsetbits_le32(reg + bpd->bus_prot_set, mask, mask);
+	else
+		writel(mask, reg + bpd->bus_prot_set);
+
+	return readl_poll_timeout(reg + bpd->bus_prot_sta, val, (val & mask) == mask, 1000);
+}
+
+static int _scpsys_bus_protect_disable(const struct mtk_scpsys_bus_prot_data *bpd,
+				       void __iomem *reg)
+{
+	u32 val = 0, mask = bpd->bus_prot_mask;
+
+	if (!mask)
+		return 0;
+
+	if (bpd->bus_prot_reg_update)
+		clrbits_le32(reg + bpd->bus_prot_clr, mask);
+	else
+		writel(mask, reg + bpd->bus_prot_clr);
+
+	if (bpd->ignore_clr_ack)
+		return 0;
+
+	return readl_poll_timeout(reg + bpd->bus_prot_sta, val, !(val & mask), 1000);
+}
+
+static int scpsys_bus_protect_enable(const struct mtk_scpsys_bus_prot_data *bpd,
+				     int bpd_size, void __iomem *reg)
 {
-	struct scp_domain *scpd = data->scpd;
-	u32 sta = readl(scpd->base + SPM_PWR_STATUS) &
-			data->sta_mask;
-	u32 sta2 = readl(scpd->base + SPM_PWR_STATUS_2ND) &
-			 data->sta_mask;
+	int ret, i;
+
+	for (i = 0; i < bpd_size; i++) {
+		ret = _scpsys_bus_protect_enable(&bpd[i], reg);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int scpsys_bus_protect_disable(const struct mtk_scpsys_bus_prot_data *bpd,
+				      int bpd_size, void __iomem *reg)
+{
+	int i, ret;
+
+	for (i = bpd_size - 1; i >= 0; i--) {
+		ret = _scpsys_bus_protect_disable(&bpd[i], reg);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+static int mtk_scpsys_domain_is_on(struct power_domain *power_domain)
+{
+	struct mtk_scpsys *scpsys = dev_get_priv(power_domain->dev);
+	const struct mtk_scp_domain_data *data = scpsys->domains[power_domain->id].data;
+	u32 spm_pwr_status = data->pwr_sta_offs ?: SPM_PWR_STATUS;
+	u32 spm_pwr_status_2nd = data->pwr_sta2nd_offs ?: SPM_PWR_STATUS_2ND;
+	u32 sta, sta2;
+
+	sta = readl(scpsys->base + spm_pwr_status) & data->sta_mask;
+	sta2 = readl(scpsys->base + spm_pwr_status_2nd) & data->sta_mask;
 
 	/*
 	 * A domain is on when both status bits are set. If only one is set
@@ -209,16 +129,40 @@ static int scpsys_domain_is_on(struct scp_domain_data *data)
 	return -EINVAL;
 }
 
-static int scpsys_power_on(struct power_domain *power_domain)
+static int mtk_scpsys_power_on(struct power_domain *power_domain)
 {
-	struct scp_domain *scpd = dev_get_priv(power_domain->dev);
-	struct scp_domain_data *data = &scpd->data[power_domain->id];
-	void __iomem *ctl_addr = scpd->base + data->ctl_offs;
-	u32 pdn_ack = data->sram_pdn_ack_bits;
+	struct mtk_scpsys *scpsys = dev_get_priv(power_domain->dev);
+	struct mtk_scp_domain *domain;
+	const struct mtk_scp_domain_data *data;
+	void __iomem *ctl_addr;
+	void __iomem *infracfg;
+	u32 pdn_ack;
 	u32 val;
 	int ret, tmp;
 
-	writel(SPM_EN, scpd->base);
+	if (power_domain->id >= scpsys->soc_data->num_domains)
+		return -EINVAL;
+
+	domain = &scpsys->domains[power_domain->id];
+	data = domain->data;
+	if (!data)
+		return -EINVAL;
+
+	ctl_addr = scpsys->base + data->ctl_offs;
+	infracfg = domain->infracfg ? domain->infracfg : scpsys->infracfg;
+	pdn_ack = data->sram_pdn_ack_bits;
+
+	if (domain->has_pd) {
+		ret = power_domain_on(&domain->parent_pd);
+		if (ret)
+			return ret;
+	}
+
+	ret = clk_enable_bulk(&domain->clks);
+	if (ret)
+		return ret;
+
+	writel(SPM_EN, scpsys->base);
 
 	val = readl(ctl_addr);
 	val |= PWR_ON_BIT;
@@ -227,7 +171,7 @@ static int scpsys_power_on(struct power_domain *power_domain)
 	val |= PWR_ON_2ND_BIT;
 	writel(val, ctl_addr);
 
-	ret = readx_poll_timeout(scpsys_domain_is_on, data, tmp, tmp > 0,
+	ret = readx_poll_timeout(mtk_scpsys_domain_is_on, power_domain, tmp, tmp > 0,
 				 100);
 	if (ret < 0)
 		return ret;
@@ -241,6 +185,10 @@ static int scpsys_power_on(struct power_domain *power_domain)
 	val |= PWR_RST_B_BIT;
 	writel(val, ctl_addr);
 
+	ret = clk_enable_bulk(&domain->subsys_clks);
+	if (ret)
+		return ret;
+
 	val &= ~data->sram_pdn_bits;
 	writel(val, ctl_addr);
 
@@ -249,31 +197,52 @@ static int scpsys_power_on(struct power_domain *power_domain)
 		return ret;
 
 	if (data->bus_prot_mask) {
-		ret = mtk_infracfg_clear_bus_protection(scpd->infracfg,
+		ret = mtk_infracfg_clear_bus_protection(infracfg,
 							data->bus_prot_mask);
 		if (ret)
 			return ret;
 	}
+	ret = scpsys_bus_protect_disable(data->bp_infracfg, SPM_MAX_BUS_PROT_DATA, infracfg);
+	if (ret < 0)
+		return ret;
 
 	return 0;
 }
 
-static int scpsys_power_off(struct power_domain *power_domain)
+static int mtk_scpsys_power_off(struct power_domain *power_domain)
 {
-	struct scp_domain *scpd = dev_get_priv(power_domain->dev);
-	struct scp_domain_data *data = &scpd->data[power_domain->id];
-	void __iomem *ctl_addr = scpd->base + data->ctl_offs;
-	u32 pdn_ack = data->sram_pdn_ack_bits;
+	struct mtk_scpsys *scpsys = dev_get_priv(power_domain->dev);
+	struct mtk_scp_domain *domain;
+	const struct mtk_scp_domain_data *data;
+	void __iomem *ctl_addr;
+	void __iomem *infracfg;
+	u32 pdn_ack;
 	u32 val;
 	int ret, tmp;
 
+	if (power_domain->id >= scpsys->soc_data->num_domains)
+		return -EINVAL;
+
+	domain = &scpsys->domains[power_domain->id];
+	data = domain->data;
+	if (!data)
+		return -EINVAL;
+
+	ctl_addr = scpsys->base + data->ctl_offs;
+	infracfg = domain->infracfg ?: scpsys->infracfg;
+	pdn_ack = data->sram_pdn_ack_bits;
+
 	if (data->bus_prot_mask) {
-		ret = mtk_infracfg_set_bus_protection(scpd->infracfg,
+		ret = mtk_infracfg_set_bus_protection(infracfg,
 						      data->bus_prot_mask);
 		if (ret)
 			return ret;
 	}
 
+	ret = scpsys_bus_protect_enable(data->bp_infracfg, SPM_MAX_BUS_PROT_DATA, infracfg);
+	if (ret < 0)
+		return ret;
+
 	val = readl(ctl_addr);
 	val |= data->sram_pdn_bits;
 	writel(val, ctl_addr);
@@ -283,6 +252,10 @@ static int scpsys_power_off(struct power_domain *power_domain)
 	if (ret < 0)
 		return ret;
 
+	ret = clk_disable_bulk(&domain->subsys_clks);
+	if (ret)
+		return ret;
+
 	val |= PWR_ISO_BIT;
 	writel(val, ctl_addr);
 
@@ -298,60 +271,38 @@ static int scpsys_power_off(struct power_domain *power_domain)
 	val &= ~PWR_ON_2ND_BIT;
 	writel(val, ctl_addr);
 
-	ret = readx_poll_timeout(scpsys_domain_is_on, data, tmp, !tmp, 100);
+	ret = readx_poll_timeout(mtk_scpsys_domain_is_on, power_domain, tmp, !tmp, 100);
 	if (ret < 0)
 		return ret;
 
-	return 0;
-}
-
-static int scpsys_power_request(struct power_domain *power_domain)
-{
-	struct scp_domain *scpd = dev_get_priv(power_domain->dev);
-	struct scp_domain_data *data;
-
-	data = &scpd->data[power_domain->id];
-	data->scpd = scpd;
-
-	return 0;
-}
-
-static int mtk_power_domain_hook(struct udevice *dev)
-{
-	struct scp_domain *scpd = dev_get_priv(dev);
-
-	scpd->type = (enum scp_domain_type)dev_get_driver_data(dev);
-
-	switch (scpd->type) {
-	case SCPSYS_MT7623:
-		scpd->data = scp_domain_mt7623;
-		break;
-	case SCPSYS_MT7622:
-	case SCPSYS_MT7629:
-		scpd->data = scp_domain_mt7629;
-		break;
-	default:
-		return -EINVAL;
-	}
+	ret = clk_disable_bulk(&domain->clks);
+	if (ret)
+		return ret;
 
 	return 0;
 }
 
-static int mtk_power_domain_probe(struct udevice *dev)
+int mtk_scpsys_probe(struct udevice *dev)
 {
 	struct ofnode_phandle_args args;
-	struct scp_domain *scpd = dev_get_priv(dev);
+	struct mtk_scpsys *scpsys = dev_get_priv(dev);
 	struct regmap *regmap;
 	struct clk_bulk bulk;
-	int err;
+	int err, i;
 
-	scpd->base = dev_read_addr_ptr(dev);
-	if (!scpd->base)
+	scpsys->base = dev_read_addr_ptr(dev);
+	if (!scpsys->base)
 		return -ENOENT;
 
-	err = mtk_power_domain_hook(dev);
-	if (err)
-		return err;
+	scpsys->soc_data = (const struct mtk_scp_soc_data *)dev_get_driver_data(dev);
+
+	scpsys->domains = devm_kcalloc(dev, scpsys->soc_data->num_domains,
+				       sizeof(*scpsys->domains), GFP_KERNEL);
+	if (!scpsys->domains)
+		return -ENOMEM;
+
+	for (i = 0; i < scpsys->soc_data->num_domains; i++)
+		scpsys->domains[i].data = &scpsys->soc_data->data[i];
 
 	/* get corresponding syscon phandle */
 	err = dev_read_phandle_with_args(dev, "infracfg", NULL, 0, 0, &args);
@@ -362,12 +313,12 @@ static int mtk_power_domain_probe(struct udevice *dev)
 	if (IS_ERR(regmap))
 		return PTR_ERR(regmap);
 
-	scpd->infracfg = regmap_get_range(regmap, 0);
-	if (!scpd->infracfg)
+	scpsys->infracfg = regmap_get_range(regmap, 0);
+	if (!scpsys->infracfg)
 		return -ENOENT;
 
 	/* enable Infra DCM */
-	setbits_le32(scpd->infracfg + INFRA_TOPDCM_CTRL, DCM_TOP_EN);
+	setbits_le32(scpsys->infracfg + INFRA_TOPDCM_CTRL, DCM_TOP_EN);
 
 	err = clk_get_bulk(dev, &bulk);
 	if (err)
@@ -376,33 +327,180 @@ static int mtk_power_domain_probe(struct udevice *dev)
 	return clk_enable_bulk(&bulk);
 }
 
-static const struct udevice_id mtk_power_domain_ids[] = {
-	{
-		.compatible = "mediatek,mt7622-scpsys",
-		.data = SCPSYS_MT7622,
-	},
-	{
-		.compatible = "mediatek,mt7623-scpsys",
-		.data = SCPSYS_MT7623,
-	},
-	{
-		.compatible = "mediatek,mt7629-scpsys",
-		.data = SCPSYS_MT7629,
-	},
-	{ /* sentinel */ }
-};
+static int mtk_scpsys_add_one_domain(struct udevice *dev, ofnode node, int parent_id)
+{
+	struct mtk_scpsys *scpsys = dev_get_priv(dev);
+	struct ofnode_phandle_args args;
+	struct mtk_scp_domain *domain;
+	struct regmap *regmap;
+	const char *clk_name;
+	int i, ret, num_clks;
+	u32 id;
 
-static const struct power_domain_ops mtk_power_domain_ops = {
-	.off = scpsys_power_off,
-	.on = scpsys_power_on,
-	.request = scpsys_power_request,
-};
+	ret = ofnode_read_u32(node, "reg", &id);
+	if (ret) {
+		dev_err(dev, "%s: failed to retrieve domain id from reg: %d\n",
+			ofnode_get_name(node), ret);
+		return ret;
+	}
+
+	if (id >= scpsys->soc_data->num_domains) {
+		dev_err(dev, "%s: invalid domain id %d\n", ofnode_get_name(node), id);
+		return -EINVAL;
+	}
+
+	domain = &scpsys->domains[id];
+	domain->data = &scpsys->soc_data->data[id];
+
+	if (parent_id >= 0) {
+		domain->has_pd = true;
+		domain->parent_pd.dev = dev;
+		domain->parent_pd.id = parent_id;
+	}
+
+	if (ofnode_read_bool(node, "mediatek,infracfg")) {
+		ret = ofnode_parse_phandle_with_args(node, "mediatek,infracfg", NULL, 0, 0, &args);
+		if (ret)
+			return ret;
+
+		regmap = syscon_node_to_regmap(args.node);
+		if (IS_ERR(regmap))
+			return PTR_ERR(regmap);
+
+		domain->infracfg = regmap_get_range(regmap, 0);
+
+		/* enable Infra DCM */
+		if (domain->infracfg)
+			setbits_le32(domain->infracfg + INFRA_TOPDCM_CTRL,
+				     DCM_TOP_EN);
+	}
+
+	num_clks = ofnode_read_string_count(node, "clock-names");
+	for (i = 0; i < num_clks; i++) {
+		ret = ofnode_read_string_index(node, "clock-names", i, &clk_name);
+		if (ret) {
+			dev_err(dev, "%s: failed to retrieve clock-names at index %i: %d\n",
+				ofnode_get_name(node), i, ret);
+			return ret;
+		}
+
+		if (strchr(clk_name, '-'))
+			domain->subsys_clks.count++;
+		else
+			domain->clks.count++;
+	}
+
+	if (domain->clks.count) {
+		domain->clks.clks = devm_kcalloc(dev, domain->clks.count,
+						 sizeof(struct clk), GFP_KERNEL);
+		if (!domain->clks.clks)
+			return -ENOMEM;
+	}
+
+	if (domain->subsys_clks.count) {
+		domain->subsys_clks.clks = devm_kcalloc(dev,
+							domain->subsys_clks.count,
+							sizeof(struct clk), GFP_KERNEL);
+		if (!domain->subsys_clks.clks)
+			return -ENOMEM;
+	}
+
+	for (i = 0; i < domain->clks.count; i++) {
+		ret = clk_get_by_index_nodev(node, i, &domain->clks.clks[i]);
+		if (ret < 0) {
+			dev_err(dev, "%s: failed to get clk at index %d: %d\n",
+				ofnode_get_name(node), i, ret);
+			goto err_put_clocks;
+		}
+	}
+
+	for (i = 0; i < domain->subsys_clks.count; i++) {
+		ret = clk_get_by_index_nodev(node, i + domain->clks.count,
+					     &domain->subsys_clks.clks[i]);
+		if (ret < 0) {
+			dev_err(dev, "%s: failed to get subsys clk at index %d: %d\n",
+				ofnode_get_name(node), i + domain->clks.count, ret);
+			goto err_put_subsys_clocks;
+		}
+	}
+
+	return 0;
+
+err_put_subsys_clocks:
+	clk_release_all(domain->subsys_clks.clks, domain->subsys_clks.count);
+	domain->subsys_clks.count = 0;
+err_put_clocks:
+	clk_release_all(domain->clks.clks, domain->clks.count);
+	domain->clks.count = 0;
+	domain->data = NULL;
+	return ret;
+}
+
+static int mtk_scpsys_add_subdomain(struct udevice *dev, ofnode node)
+{
+	ofnode subnode;
+	int ret;
+	u32 id;
+
+	ret = ofnode_read_u32(node, "reg", &id);
+	if (ret) {
+		dev_err(dev, "%s: failed to get domain id\n", ofnode_get_name(node));
+		return ret;
+	}
+
+	ofnode_for_each_subnode(subnode, node) {
+		ret = mtk_scpsys_add_one_domain(dev, subnode, id);
+		if (ret) {
+			dev_err(dev, "failed to add child domain: %s\n",
+				ofnode_get_name(subnode));
+			continue;
+		}
+
+		ret = mtk_scpsys_add_subdomain(dev, subnode);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+}
+
+int mtk_power_controller_probe(struct udevice *dev)
+{
+	struct mtk_scpsys *scpsys = dev_get_priv(dev);
+	ofnode subnode;
+	int ret;
+
+	scpsys->base = dev_read_addr_ptr(dev_get_parent(dev));
+	if (!scpsys->base)
+		return -ENOENT;
+
+	scpsys->soc_data = (const struct mtk_scp_soc_data *)dev_get_driver_data(dev);
+
+	scpsys->domains = devm_kcalloc(dev, scpsys->soc_data->num_domains,
+				       sizeof(*scpsys->domains), GFP_KERNEL);
+	if (!scpsys->domains)
+		return -ENOMEM;
+
+	dev_for_each_subnode(subnode, dev) {
+		ret = mtk_scpsys_add_one_domain(dev, subnode, -1);
+		if (ret) {
+			dev_err(dev, "failed to add child domain: %s\n",
+				ofnode_get_name(subnode));
+			continue;
+		}
+
+		ret = mtk_scpsys_add_subdomain(dev, subnode);
+		if (ret) {
+			dev_err(dev, "failed to add sub domain: %s\n",
+				ofnode_get_name(subnode));
+			return ret;
+		}
+	}
+
+	return 0;
+}
 
-U_BOOT_DRIVER(mtk_power_domain) = {
-	.name = "mtk_power_domain",
-	.id = UCLASS_POWER_DOMAIN,
-	.ops = &mtk_power_domain_ops,
-	.probe = mtk_power_domain_probe,
-	.of_match = mtk_power_domain_ids,
-	.priv_auto	= sizeof(struct scp_domain),
+const struct power_domain_ops mtk_power_domain_ops = {
+	.off = mtk_scpsys_power_off,
+	.on = mtk_scpsys_power_on,
 };
diff --git a/drivers/power/domain/mtk-power-domain.h b/drivers/power/domain/mtk-power-domain.h
new file mode 100644
index 00000000000..5bf0ca850ec
--- /dev/null
+++ b/drivers/power/domain/mtk-power-domain.h
@@ -0,0 +1,131 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2018 MediaTek Inc.
+ * Copyright (C) 2026 BayLibre, SAS
+ * Author: Ryder Lee <[email protected]>
+ *         Julien Stephan <[email protected]>
+ */
+
+#ifndef __MTK_POWER_DOMAIN_H
+#define __MTK_POWER_DOMAIN_H
+
+#include <clk.h>
+#include <power-domain-uclass.h>
+#include <linux/bitops.h>
+#include <linux/compiler.h>
+#include <linux/kernel.h>
+#include <linux/types.h>
+
+struct udevice;
+
+#define SPM_EN			(0xb16 << 16 | 0x1)
+#define SPM_VDE_PWR_CON		0x0210
+#define SPM_MFG_PWR_CON		0x0214
+#define SPM_ISP_PWR_CON		0x0238
+#define SPM_DIS_PWR_CON		0x023c
+#define SPM_CONN_PWR_CON	0x0280
+#define SPM_BDP_PWR_CON		0x029c
+#define SPM_ETH_PWR_CON		0x02a0
+#define SPM_HIF_PWR_CON		0x02a4
+#define SPM_IFR_MSC_PWR_CON	0x02a8
+#define SPM_ETHSYS_PWR_CON	0x2e0
+#define SPM_HIF0_PWR_CON	0x2e4
+#define SPM_HIF1_PWR_CON	0x2e8
+#define SPM_PWR_STATUS		0x60c
+#define SPM_PWR_STATUS_2ND	0x610
+
+#define PWR_RST_B_BIT		BIT(0)
+#define PWR_ISO_BIT		BIT(1)
+#define PWR_ON_BIT		BIT(2)
+#define PWR_ON_2ND_BIT		BIT(3)
+#define PWR_CLK_DIS_BIT		BIT(4)
+
+#define PWR_STATUS_CONN		BIT(1)
+#define PWR_STATUS_DISP		BIT(3)
+#define PWR_STATUS_MFG		BIT(4)
+#define PWR_STATUS_ISP		BIT(5)
+#define PWR_STATUS_VDEC		BIT(7)
+#define PWR_STATUS_BDP		BIT(14)
+#define PWR_STATUS_ETH		BIT(15)
+#define PWR_STATUS_HIF		BIT(16)
+#define PWR_STATUS_IFR_MSC	BIT(17)
+#define PWR_STATUS_ETHSYS	BIT(24)
+#define PWR_STATUS_HIF0		BIT(25)
+#define PWR_STATUS_HIF1		BIT(26)
+
+/* Infrasys configuration */
+#define INFRA_TOPDCM_CTRL	0x10
+#define INFRA_TOPAXI_PROT_EN	0x220
+#define INFRA_TOPAXI_PROT_STA1	0x228
+
+#define DCM_TOP_EN		BIT(0)
+
+#define SPM_MAX_BUS_PROT_DATA	6
+
+struct mtk_scp_domain;
+
+struct mtk_scpsys_bus_prot_data {
+	u32 bus_prot_mask;
+	u32 bus_prot_set;
+	u32 bus_prot_clr;
+	u32 bus_prot_sta;
+	bool bus_prot_reg_update;
+	bool ignore_clr_ack;
+};
+
+struct mtk_scp_domain_data {
+	u32 sta_mask;
+	int ctl_offs;
+	u32 sram_pdn_bits;
+	u32 sram_pdn_ack_bits;
+	u32 bus_prot_mask;
+	const struct mtk_scpsys_bus_prot_data bp_infracfg[SPM_MAX_BUS_PROT_DATA];
+	int pwr_sta_offs;
+	int pwr_sta2nd_offs;
+};
+
+struct mtk_scp_soc_data {
+	const struct mtk_scp_domain_data *data;
+	int num_domains;
+};
+
+#define MTK_SCP_SOC_DATA(_name, _domains)			\
+static const struct mtk_scp_soc_data _name##_scp_soc_data = {	\
+	.data = _domains,					\
+	.num_domains = ARRAY_SIZE(_domains),			\
+}
+
+struct mtk_scp_domain {
+	const struct mtk_scp_domain_data *data;
+	void __iomem *infracfg;
+	struct clk_bulk clks;
+	struct clk_bulk subsys_clks;
+	bool has_pd;
+	struct power_domain parent_pd;
+};
+
+struct mtk_scpsys {
+	void __iomem *base;
+	void __iomem *infracfg;
+	const struct mtk_scp_soc_data *soc_data;
+	struct mtk_scp_domain *domains;
+};
+
+#define _BUS_PROT(_mask, _set, _clr, _sta, _update, _ignore) {	\
+	.bus_prot_mask = (_mask),				\
+	.bus_prot_set = (_set),					\
+	.bus_prot_clr = (_clr),					\
+	.bus_prot_sta = (_sta),					\
+	.bus_prot_reg_update = (_update),			\
+	.ignore_clr_ack = (_ignore),				\
+}
+
+#define BUS_PROT_WR(_mask, _set, _clr, _sta)			\
+	_BUS_PROT(_mask, _set, _clr, _sta, false, false)
+
+int mtk_scpsys_probe(struct udevice *dev);
+int mtk_power_controller_probe(struct udevice *dev);
+
+extern const struct power_domain_ops mtk_power_domain_ops;
+
+#endif /* __MTK_POWER_DOMAIN_H */
author	Tom Rini <[email protected]>	2026-07-23 10:55:18 -0600
committer	Tom Rini <[email protected]>	2026-07-23 10:55:18 -0600
commit	88226db737b258c36141b66dabe5542b2407f5cd (patch)
tree	c5b58e3f7dba5fca5c71c8cb1996bcba0b1057c9
parent	a814edb52d93b6355c9ea1cb86ce29adb32ebbc2 (diff)
parent	d0c49353a648e135f269a2953dc9326505ba87de (diff)