diff options
| author | York Sun <[email protected]> | 2016-07-29 09:02:29 -0700 |
|---|---|---|
| committer | York Sun <[email protected]> | 2016-08-02 09:47:34 -0700 |
| commit | 8936691ba69bc322201c62e977e2803cfe67fc40 (patch) | |
| tree | 2c7aa873b2e5068cfc3aeefd2022719dc0e06fff | |
| parent | 473af36a889d3a7e6faad1ec95b926a21c834bf8 (diff) | |
driver/ddr/fsl: Fix timing_cfg_2
Commit 5605dc6 tried to fix wr_lat bit in timing_cfg_2, but the
change was wrong. wr_lat has 5 bits with MSB at [13] and lower
4 bits at [9:12], in big-endian convention.
Signed-off-by: York Sun <[email protected]>
Reported-by: Thomas Schaefer <[email protected]>
| -rw-r--r-- | drivers/ddr/fsl/ctrl_regs.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index abd576b9350..24fd36602d2 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -709,7 +709,7 @@ static void set_timing_cfg_2(const unsigned int ctrl_num, | ((add_lat_mclk & 0xf) << 28) | ((cpo & 0x1f) << 23) | ((wr_lat & 0xf) << 19) - | ((wr_lat & 0x10) << 18) + | (((wr_lat & 0x10) >> 4) << 18) | ((rd_to_pre & RD_TO_PRE_MASK) << RD_TO_PRE_SHIFT) | ((wr_data_delay & WR_DATA_DELAY_MASK) << WR_DATA_DELAY_SHIFT) | ((cke_pls & 0x7) << 6) |