diff options
| author | Ken Ma <[email protected]> | 2018-03-26 15:56:00 +0800 |
|---|---|---|
| committer | Stefan Roese <[email protected]> | 2018-03-30 12:52:48 +0200 |
| commit | 8aecbcd166d8ce81556e9bb4ab6b160f18a524d1 (patch) | |
| tree | c7c936791d36a9128ce3f2e8a88a1ba68809bfea | |
| parent | 44ac747bdfceeefdf3cd70caed05eddfe23affb8 (diff) | |
arm64: a37xx: dts: Fix the number of GPIO on south bridge
The number of pins in South Bridge is 30 and not 29. There is a fix for
the driver for the pinctrl, but a fix is also need at device tree level
for the GPIO.
Reviewed-on: http://vgitil04.il.marvell.com:8080/43286
Reviewed-by: Hua Jing <[email protected]>
Tested-by: iSoC Platform CI <[email protected]>
Cc: Simon Glass <[email protected]>
Cc: Stefan Roese <[email protected]>
Signed-off-by: Ken Ma <[email protected]>
Signed-off-by: Stefan Roese <[email protected]>
| -rw-r--r-- | arch/arm/dts/armada-37xx.dtsi | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/dts/armada-37xx.dtsi b/arch/arm/dts/armada-37xx.dtsi index fab95bbc123..d139a617a98 100644 --- a/arch/arm/dts/armada-37xx.dtsi +++ b/arch/arm/dts/armada-37xx.dtsi @@ -168,7 +168,7 @@ reg = <0x18800 0x100>, <0x18C00 0x20>; gpiosb: gpiosb { #gpio-cells = <2>; - gpio-ranges = <&pinctrl_sb 0 0 29>; + gpio-ranges = <&pinctrl_sb 0 0 30>; gpio-controller; interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, |