Merge branch 'main' of https://git.u-boot-project.org/u-boot/custodians/u-boot-sh

This includes temporary U-Boot DT ECC carveouts for R-Car Gen5, they
will be dropped from U-Boot DTs once OF_UPSTREAM DTs get re-synced.
This also includes RPC-IF support for R-Car Gen5 and env storage in RPC
HF.
This also includes an update for R-Car Gen5 UFS controller driver.

8 files changed, 157 insertions, 33 deletions

diff --git a/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi b/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi
index 356f633135d..872cbfdbad6 100644
--- a/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi
+++ b/arch/arm/dts/r8a78000-ironhide-cm33-u-boot.dtsi
@@ -70,6 +70,23 @@
 		reg = <0 0xb8940000 0 0xf000>;
 	};
 
+	spi@c08c0000 {
+		compatible = "renesas,r8a78000-rpc-if",
+			     "renesas,rcar-gen5-rpc-if";
+		reg = <0 0xc08c0000 0 0x200>,
+		      <0 0x34000000 0 0x04000000>,
+		      <0 0xc08c8000 0 0x100>;
+		reg-names = "regs", "dirmap", "wbuf";
+		clocks = <&dummy_clk_rclk>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		flash@0 {
+			compatible = "cypress,hyperflash", "cfi-flash";
+			reg = <0>;
+		};
+	};
+
 	scp@c1340000 {
 		compatible = "renesas,r8a78000-rproc";
 		reg = <0 0xc1340000 0 0x80000>;
diff --git a/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi b/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi
index 299716f96a4..2dc8ad7aa6b 100644
--- a/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi
+++ b/arch/arm/dts/r8a78000-ironhide-u-boot.dtsi
@@ -15,6 +15,13 @@
 		mmc0 = &mmc0;
 	};
 
+	/delete-node/ memory@60600000;
+
+	memory@40000000 {
+		device_type = "memory";
+		reg = <0x0 0x40000000 0x0 0x80000000>;
+	};
+
 	reg_1p8v: regulator-1p8v {
 		compatible = "regulator-fixed";
 		regulator-name = "fixed-1.8V";
@@ -32,6 +39,77 @@
 		regulator-boot-on;
 		regulator-always-on;
 	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* First 518 MiB is reserved for other purposes. */
+		firmware@40000000 {
+			reg = <0x0 0x40000000 0x0 0x20600000>;
+			no-map;
+		};
+
+		/* Parameters set by IPL. */
+		parameters@8c100000 {
+			reg = <0x0 0x8c100000 0x0 0x00008000>;
+			no-map;
+		};
+
+		/* TFA BL31. */
+		tfa-bl31@8c200000 {
+			reg = <0x0 0x8c200000 0x0 0x00080000>;
+			no-map;
+		};
+
+		/* TEE TZ DRAM. */
+		tee@8c400000 {
+			reg = <0x0 0x8c400000 0x0 0x02000000>;
+			no-map;
+		};
+
+		/* DRAM controller inline ECC areas */
+		ecc@10cccc0000 {
+			reg = <0x10 0xcccc0000 0x0 0x33340000>;
+			no-map;
+		};
+
+		ecc@12cccc0000 {
+			reg = <0x12 0xcccc0000 0x0 0x33340000>;
+			no-map;
+		};
+
+		ecc@14cccc0000 {
+			reg = <0x14 0xcccc0000 0x0 0x33340000>;
+			no-map;
+		};
+
+		ecc@16cccc0000 {
+			reg = <0x16 0xcccc0000 0x0 0x33340000>;
+			no-map;
+		};
+
+		ecc@18cccc0000 {
+			reg = <0x18 0xcccc0000 0x0 0x33340000>;
+			no-map;
+		};
+
+		ecc@1a66660000 {
+			reg = <0x1a 0x66660000 0x0 0x999a0000>;
+			no-map;
+		};
+
+		ecc@1c66660000 {
+			reg = <0x1c 0x66660000 0x0 0x999a0000>;
+			no-map;
+		};
+
+		ecc@1e66660000 {
+			reg = <0x1e 0x66660000 0x0 0x999a0000>;
+			no-map;
+		};
+	};
 };
 
 &cpg {
diff --git a/configs/r8a78000_ironhide_cm33_defconfig b/configs/r8a78000_ironhide_cm33_defconfig
index 7ea3ae993ba..618712385ad 100644
--- a/configs/r8a78000_ironhide_cm33_defconfig
+++ b/configs/r8a78000_ironhide_cm33_defconfig
@@ -20,6 +20,8 @@ CONFIG_BAUDRATE=1843200
 CONFIG_BOARD_EARLY_INIT_R=y
 CONFIG_BOOTCOMMAND="run rsip_ipl_boot_ca0"
 CONFIG_BOUNCE_BUFFER=y
+CONFIG_CFI_FLASH=y
+CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS=y
 CONFIG_CMD_IMI=y
 CONFIG_CMD_PSTORE=y
 CONFIG_CMD_PSTORE_MEM_ADDR=0x80000000
@@ -29,10 +31,19 @@ CONFIG_CMD_REMOTEPROC=y
 CONFIG_CMD_UFS=y
 CONFIG_DM_DMA=y
 CONFIG_DM_ETH_PHY=y
+CONFIG_DM_MTD=y
 CONFIG_DM_RESET=y
-CONFIG_ENV_SIZE=0x20000
+CONFIG_ENV_ADDR=0x37F80000
+CONFIG_ENV_ADDR_REDUND=0x37FC0000
+CONFIG_ENV_IS_IN_FLASH=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_REDUNDANT=y
+CONFIG_ENV_SECT_SIZE=0x40000
+CONFIG_ENV_SIZE=0x40000
+CONFIG_FLASH_CFI_MTD=y
 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
 CONFIG_LAST_STAGE_INIT=y
+CONFIG_MTD_NOR_FLASH=y
 CONFIG_NET_LWIP=y
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_NR_DRAM_BANKS=1
@@ -46,6 +57,7 @@ CONFIG_RAM_RENESAS_DBSC5=y
 CONFIG_REMOTEPROC_RENESAS_RSIP=y
 CONFIG_RENESAS_ETHER_SWITCH=y
 CONFIG_RENESAS_R8A78000_POWER_DOMAIN=y
+CONFIG_RENESAS_RPC_HF=y
 CONFIG_SCSI=y
 CONFIG_SERIAL_PROBE_ALL=y
 CONFIG_SF_DEFAULT_SPEED=40000000
@@ -55,8 +67,14 @@ CONFIG_SYS_ARCH_TIMER=y
 CONFIG_SYS_BARGSIZE=2048
 CONFIG_SYS_BOOT_GET_CMDLINE=y
 CONFIG_SYS_CLK_FREQ=16666666
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_SYS_FLASH_CFI_WIDTH_16BIT=y
+CONFIG_SYS_FLASH_PROTECTION=y
+CONFIG_SYS_FLASH_QUIET_TEST=y
 CONFIG_SYS_LOAD_ADDR=0xb8000000
 CONFIG_SYS_MALLOC_LEN=0x80000
+CONFIG_SYS_MAX_FLASH_BANKS_DETECT=y
+CONFIG_SYS_MAX_FLASH_SECT=256
 CONFIG_SYS_TIMER_COUNTS_DOWN=y
 CONFIG_UFS=y
 CONFIG_UFS_RENESAS_GEN5=y
@@ -75,7 +93,9 @@ CONFIG_WDT_RENESAS_WWDT=y
 # CONFIG_OF_UPSTREAM is not set
 # CONFIG_BOARD_EARLY_INIT_F is not set
 # CONFIG_OF_BOARD_SETUP is not set
+# CONFIG_RENESAS_RPC_SPI is not set
 # CONFIG_SYS_ARCH_TIMER is not set
+# CONFIG_MMC is not set
 
 CONFIG_DEBUG_UART=y
 CONFIG_DEBUG_UART_SCIF=y
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 38d6dd142dd..f6bd9f6f2e9 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -196,7 +196,7 @@ config ALTERA_QSPI
 
 config RENESAS_RPC_HF
 	bool "Renesas R-Car Gen3 RPC HyperFlash driver"
-	depends on RCAR_GEN3 && DM_MTD
+	depends on RCAR_64 && DM_MTD
 	help
 	  This enables access to HyperFlash memory through the Renesas
 	  R-Car Gen3 RPC controller.
diff --git a/drivers/mtd/renesas_rpc_hf.c b/drivers/mtd/renesas_rpc_hf.c
index 9390c9e9ab3..c94a25fe6a1 100644
--- a/drivers/mtd/renesas_rpc_hf.c
+++ b/drivers/mtd/renesas_rpc_hf.c
@@ -344,21 +344,21 @@ static int rpc_hf_bind(struct udevice *parent)
 
 static int rpc_hf_probe(struct udevice *dev)
 {
-	void *blob = (void *)gd->fdt_blob;
-	const fdt32_t *cell;
-	int node = dev_of_offset(dev);
-	int parent, addrc, sizec, len, ret;
-	struct clk clk;
 	phys_addr_t flash_base;
+	struct clk clk;
+	int ret;
 
-	parent = fdt_parent_offset(blob, node);
-	fdt_support_default_count_cells(blob, parent, &addrc, &sizec);
-	cell = fdt_getprop(blob, node, "reg", &len);
-	if (!cell)
-		return -ENOENT;
+	rpc_base = dev_read_addr_name(dev, "regs");
+	if (rpc_base == FDT_ADDR_T_NONE) {
+		dev_err(dev, "Failed to get RPC control registers\n");
+		return -EINVAL;
+	}
 
-	if (addrc != 2 || sizec != 2)
+	flash_base = dev_read_addr_name(dev, "dirmap");
+	if (flash_base == FDT_ADDR_T_NONE) {
+		dev_err(dev, "Failed to get RPC direct map registers\n");
 		return -EINVAL;
+	}
 
 	ret = clk_get_by_index(dev, 0, &clk);
 	if (ret < 0) {
@@ -372,9 +372,6 @@ static int rpc_hf_probe(struct udevice *dev)
 		return ret;
 	}
 
-	rpc_base = fdt_translate_address(blob, node, cell);
-	flash_base = fdt_translate_address(blob, node, cell + addrc + sizec);
-
 	flash_info[0].dev = dev;
 	flash_info[0].base = flash_base;
 	cfi_flash_num_flash_banks = 1;
@@ -387,6 +384,7 @@ static const struct udevice_id rpc_hf_ids[] = {
 	{ .compatible = "renesas,r7s72100-rpc-if" },
 	{ .compatible = "renesas,rcar-gen3-rpc-if" },
 	{ .compatible = "renesas,rcar-gen4-rpc-if" },
+	{ .compatible = "renesas,rcar-gen5-rpc-if" },
 	{}
 };
 
diff --git a/drivers/spi/renesas_rpc_spi.c b/drivers/spi/renesas_rpc_spi.c
index 7103d786c7e..76eca5389a2 100644
--- a/drivers/spi/renesas_rpc_spi.c
+++ b/drivers/spi/renesas_rpc_spi.c
@@ -145,11 +145,11 @@
 #define RPC_PHYCNT_WBUF		BIT(2)
 #define RPC_PHYCNT_MEM(v)	(((v) & 0x3) << 0)
 
-#define RPCIF_PHYOFFSET1	0x0080	/* R/W */
-#define RPCIF_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
+#define RPC_PHYOFFSET1	0x0080	/* R/W */
+#define RPC_PHYOFFSET1_DDRTMG(v) (((v) & 0x3) << 28)
 
-#define RPCIF_PHYOFFSET2	0x0084	/* R/W */
-#define RPCIF_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
+#define RPC_PHYOFFSET2	0x0084	/* R/W */
+#define RPC_PHYOFFSET2_OCTTMG(v) (((v) & 0x7) << 8)
 
 #define RPC_PHYINT		0x0088	/* R/W */
 #define RPC_PHYINT_RSTEN	BIT(18)
@@ -233,11 +233,11 @@ static int rpc_spi_claim_bus(struct udevice *dev, bool manual)
 	struct udevice *bus = dev->parent;
 	struct rpc_spi_priv *priv = dev_get_priv(bus);
 
-	setbits_le32(priv->regs + RPCIF_PHYOFFSET1,
-		     RPCIF_PHYOFFSET1_DDRTMG(3));
-	clrsetbits_le32(priv->regs + RPCIF_PHYOFFSET2,
-			RPCIF_PHYOFFSET2_OCTTMG(7),
-			RPCIF_PHYOFFSET2_OCTTMG(4));
+	setbits_le32(priv->regs + RPC_PHYOFFSET1,
+		     RPC_PHYOFFSET1_DDRTMG(3));
+	clrsetbits_le32(priv->regs + RPC_PHYOFFSET2,
+			RPC_PHYOFFSET2_OCTTMG(7),
+			RPC_PHYOFFSET2_OCTTMG(4));
 
 	/* NOTE: The 0x260 are undocumented bits, but they must be set. */
 	writel(RPC_PHYCNT_CAL | rpc_spi_get_strobe_delay() | 0x260,
@@ -466,6 +466,7 @@ static const struct udevice_id rpc_spi_ids[] = {
 	{ .compatible = "renesas,r7s72100-rpc-if" },
 	{ .compatible = "renesas,rcar-gen3-rpc-if" },
 	{ .compatible = "renesas,rcar-gen4-rpc-if" },
+	{ .compatible = "renesas,rcar-gen5-rpc-if" },
 	{ }
 };
 
diff --git a/drivers/ufs/ufs-renesas-rcar-gen5.c b/drivers/ufs/ufs-renesas-rcar-gen5.c
index a9473cd60b1..c6e436fe197 100644
--- a/drivers/ufs/ufs-renesas-rcar-gen5.c
+++ b/drivers/ufs/ufs-renesas-rcar-gen5.c
@@ -72,7 +72,7 @@ static int ufs_renesas_pre_init(struct ufs_hba *hba)
 	if (ret)
 		return ret;
 
-	writew(0x0000, priv->phy_base + 0x20000);
+	clrbits_le16(priv->phy_base + 0x20000, BIT(0));
 
 	ufshcd_writel(hba, BIT(0), REG_CONTROLLER_ENABLE);
 
@@ -88,6 +88,9 @@ static int ufs_renesas_pre_init(struct ufs_hba *hba)
 	if (ret)
 		return ret;
 
+	ufshcd_rmwl(hba, 0xe000, 0, 0xc0);
+	ufshcd_rmwl(hba, 0x5000, 0x5000, 0xc0);
+
 	/* Skip IE because we cannot handle interrupts here */
 	ufs_dme_command(hba, 0x00000002, 0x81010000, 0x00000000, 0x00000005);
 	ufs_dme_command(hba, 0x00000002, 0x81150000, 0x00000000, 0x00000001);
@@ -133,6 +136,10 @@ static int ufs_renesas_pre_init(struct ufs_hba *hba)
 	if (ret)
 		return ret;
 
+	clrbits_le16(priv->phy_base + 0x20000, BIT(0));
+
+	ufs_dme_command(hba, 0x00000002, 0xd0890000, 0x00000000, 0x00000001);
+
 	priv->initialized = true;
 
 	return 0;
@@ -140,8 +147,7 @@ static int ufs_renesas_pre_init(struct ufs_hba *hba)
 
 static int ufs_renesas_init(struct ufs_hba *hba)
 {
-	hba->quirks |= UFSHCD_QUIRK_BROKEN_64BIT_ADDRESS | UFSHCD_QUIRK_HIBERN_FASTAUTO |
-		       UFSHCD_QUIRK_BROKEN_LCC;
+	hba->quirks |= UFSHCD_QUIRK_HIBERN_FASTAUTO | UFSHCD_QUIRK_BROKEN_LCC;
 
 	return 0;
 }
@@ -180,12 +186,12 @@ static int ufs_renesas_get_max_pwr_mode(struct ufs_hba *hba,
 {
 	max_pwr_info->info.gear_rx = UFS_HS_G5;
 	max_pwr_info->info.gear_tx = UFS_HS_G5;
-	max_pwr_info->info.pwr_tx = FASTAUTO_MODE;
-	max_pwr_info->info.pwr_rx = FASTAUTO_MODE;
-	max_pwr_info->info.hs_rate = PA_HS_MODE_A;
+	max_pwr_info->info.pwr_tx = FAST_MODE;
+	max_pwr_info->info.pwr_rx = FAST_MODE;
+	max_pwr_info->info.hs_rate = PA_HS_MODE_B;
 
-	max_pwr_info->info.lane_rx = 1;
-	max_pwr_info->info.lane_tx = 1;
+	max_pwr_info->info.lane_rx = 2;
+	max_pwr_info->info.lane_tx = 2;
 
 	dev_info(hba->dev, "Max HS Gear: %d\n", max_pwr_info->info.gear_rx);
 
diff --git a/include/configs/rcar-gen5-common.h b/include/configs/rcar-gen5-common.h
index a0c05521c85..8ccd823cf53 100644
--- a/include/configs/rcar-gen5-common.h
+++ b/include/configs/rcar-gen5-common.h
@@ -27,6 +27,10 @@
 #define CFG_SYS_TIMER_COUNTER		(TMU_BASE + 0xc)	/* TCNT0 */
 #define CFG_SYS_TIMER_RATE		(133333333 / 4)
 
+/* HyperFlash */
+#define CFG_SYS_FLASH_BANKS_LIST	{ 0x34000000 }
+#define CFG_SYS_WRITE_SWAPPED_DATA
+
 /* Environment setting */
 #define CFG_EXTRA_ENV_SETTINGS						\
 	"rsip_ipl_params_base=0x8c100000\0"				\