diff options
| author | Svyatoslav Ryhel <[email protected]> | 2024-01-23 19:16:20 +0200 |
|---|---|---|
| committer | Anatolij Gustschin <[email protected]> | 2024-04-21 09:07:01 +0200 |
| commit | 97b6914e2b125ae47ae6711cb0975a18b75c1634 (patch) | |
| tree | 48832d610d61ee6e3a029ae66083c63ac7ef7dc5 | |
| parent | b9ef623c1145c3897deef009c860c0576bc6a310 (diff) | |
video: tegra20: dc: add PLLD2 parent support
T30+ SOC have second PLLD - PLLD2 which can be actively used by
DC and act as main DISP1/2 clock parent.
Tested-by: Agneli <[email protected]> # Toshiba AC100 T20
Tested-by: Robert Eckelmann <[email protected]> # ASUS TF101
Tested-by: Andreas Westman Dorcsak <[email protected]> # ASUS Grouper E1565
Tested-by: Ion Agorria <[email protected]> # HTC One X
Tested-by: Svyatoslav Ryhel <[email protected]> # Nvidia Tegratab T114
Signed-off-by: Svyatoslav Ryhel <[email protected]>
Reviewed-by: Thierry Reding <[email protected]>
| -rw-r--r-- | drivers/video/tegra20/tegra-dc.c | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/drivers/video/tegra20/tegra-dc.c b/drivers/video/tegra20/tegra-dc.c index 0e94e665efc..56a23b3c979 100644 --- a/drivers/video/tegra20/tegra-dc.c +++ b/drivers/video/tegra20/tegra-dc.c @@ -304,6 +304,12 @@ static int tegra_display_probe(struct tegra_lcd_priv *priv, if (priv->dc_clk[1] == CLOCK_ID_DISPLAY) rate /= 2; +#ifndef CONFIG_TEGRA20 + /* PLLD2 obeys same rules as PLLD but it is present only on T30+ */ + if (priv->dc_clk[1] == CLOCK_ID_DISPLAY2) + rate /= 2; +#endif + /* * HOST1X is init by default at 150MHz with PLLC as parent */ |