diff options
| author | Patrice Chotard <[email protected]> | 2018-01-19 18:02:40 +0100 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2018-01-28 09:39:15 -0500 |
| commit | 990dba649852d79a3ac5f9540a713f6207cf7ea8 (patch) | |
| tree | fd36d56ba6c9e344287fa52d73134b8c6842d83c | |
| parent | a93feb2edc60b9db76ec794bff5ad0fcb10ce3eb (diff) | |
clk: clk_stm32f: Fix PLLSAICFGR_PLLSAIP_4 divider value
PLLSAIP divider uses 2 bits (bits 16 and 17) into RCC_PLLSAICFGR
register, available combination are :
00: PLLSAIP = 2
01: PLLSAIP = 4
10: PLLSAIP = 6
11: PLLSAIP = 8
Previously, the divider value was incorrectly set to 6.
Signed-off-by: Patrice Chotard <[email protected]>
| -rw-r--r-- | drivers/clk/clk_stm32f.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/clk/clk_stm32f.c b/drivers/clk/clk_stm32f.c index 8d0f9d42664..06827fec752 100644 --- a/drivers/clk/clk_stm32f.c +++ b/drivers/clk/clk_stm32f.c @@ -59,7 +59,7 @@ #define RCC_PLLCFGR_PLLSAIP_MASK GENMASK(17, 16) #define RCC_PLLSAICFGR_PLLSAIN_SHIFT 6 #define RCC_PLLSAICFGR_PLLSAIP_SHIFT 16 -#define RCC_PLLSAICFGR_PLLSAIP_4 BIT(17) +#define RCC_PLLSAICFGR_PLLSAIP_4 BIT(16) #define RCC_PLLSAICFGR_PLLSAIQ_4 BIT(26) #define RCC_PLLSAICFGR_PLLSAIR_2 BIT(29) |