diff options
| author | Dinh Nguyen <[email protected]> | 2017-04-26 23:36:03 -0500 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2017-05-15 10:38:04 -0400 |
| commit | 9ad7147b8d38f00df1d81e237f5cfad0a0e3a39b (patch) | |
| tree | 02d0cfe2ec06aa02fac53940546eb2c2544e1445 | |
| parent | 22f3368e71321db1e0e15dfbf54b052367890ec7 (diff) | |
armv8: minor fix to comment for enabling SMPEN bit
The SMPEN bit is located in the cpuectlr_el1 register and not the
cpuactlr_el1 register. Adjust the comment accordingly and also fix
a spelling error.
Signed-off-by: Dinh Nguyen <[email protected]>
CC: Mingkai Hu <[email protected]>
CC: Gong Qianyu <[email protected]>
CC: Mateusz Kulikowski <[email protected]>
CC: Hou Zhiqiang <[email protected]>
CC: York Sun <[email protected]>
CC: Albert Aribaud <[email protected]>
CC: Masahiro Yamada <[email protected]>
Reviewed-by: York Sun <[email protected]>
| -rw-r--r-- | arch/arm/cpu/armv8/start.S | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/armv8/start.S b/arch/arm/cpu/armv8/start.S index 62d97f7e882..354468b9053 100644 --- a/arch/arm/cpu/armv8/start.S +++ b/arch/arm/cpu/armv8/start.S @@ -86,12 +86,12 @@ save_boot_params_ret: 0: /* - * Enalbe SMPEN bit for coherency. + * Enable SMPEN bit for coherency. * This register is not architectural but at the moment * this bit should be set for A53/A57/A72. */ #ifdef CONFIG_ARMV8_SET_SMPEN - mrs x0, S3_1_c15_c2_1 /* cpuactlr_el1 */ + mrs x0, S3_1_c15_c2_1 /* cpuectlr_el1 */ orr x0, x0, #0x40 msr S3_1_c15_c2_1, x0 #endif |