summaryrefslogtreecommitdiff
diff options
context:
space:
mode:
authorMax Krummenacher <[email protected]>2024-01-17 11:16:46 +0100
committerTom Rini <[email protected]>2024-01-24 11:12:11 -0500
commita1f466a9400a5e9570909414af7dc4681284c444 (patch)
tree285530142e39c54d95929e75efb80a64fe2298db
parente2e69291ee6031eccf50113fdd12099a1a7d44ba (diff)
board: verdin-am62: improve comment on usb phy core voltage
TI recommends to clear the bit independent of the used voltage. So the comment which claims to do it due to the core voltage at 0.85V is bogus. See https://e2e.ti.com/support/processors-group/processors/f/processors-forum/1252724/am625-usb-phy-core-voltage-selection-and-vdda_core_usb-mismatch Signed-off-by: Max Krummenacher <[email protected]>
-rw-r--r--board/toradex/verdin-am62/verdin-am62.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/board/toradex/verdin-am62/verdin-am62.c b/board/toradex/verdin-am62/verdin-am62.c
index 2718263eb19..e948fc16ba9 100644
--- a/board/toradex/verdin-am62/verdin-am62.c
+++ b/board/toradex/verdin-am62/verdin-am62.c
@@ -102,12 +102,13 @@ void spl_board_init(void)
{
u32 val;
- /* Set USB0 PHY core voltage to 0.85V */
+ /* Clear USB0_PHY_CTRL_CORE_VOLTAGE */
+ /* TI recommends to clear the bit independent of VDDA_CORE_USB */
val = readl(CTRLMMR_USB0_PHY_CTRL);
val &= ~(CORE_VOLTAGE);
writel(val, CTRLMMR_USB0_PHY_CTRL);
- /* Set USB1 PHY core voltage to 0.85V */
+ /* Clear USB1_PHY_CTRL_CORE_VOLTAGE */
val = readl(CTRLMMR_USB1_PHY_CTRL);
val &= ~(CORE_VOLTAGE);
writel(val, CTRLMMR_USB1_PHY_CTRL);