diff options
| author | Nikhil M Jain <[email protected]> | 2023-07-18 14:27:35 +0530 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2023-07-21 15:32:12 -0400 |
| commit | a72532fa194ed31b559bdd8b287854df0a4903f8 (patch) | |
| tree | b6981028f79b40cc7a85b8bb615704edcb23d66f | |
| parent | 1f7682383f4334afc21ea62b072392955d201d62 (diff) | |
doc: board: ti: am62x_sk: Add A53 SPL DDR layout
To understand usage of DDR in A53 SPL stage, add a table showing region
and space used by major components of SPL.
Signed-off-by: Nikhil M Jain <[email protected]>
Reviewed-by: Tom Rini <[email protected]>
| -rw-r--r-- | doc/board/ti/am62x_sk.rst | 57 |
1 files changed, 57 insertions, 0 deletions
diff --git a/doc/board/ti/am62x_sk.rst b/doc/board/ti/am62x_sk.rst index 27d7b527c6a..8642bdf16db 100644 --- a/doc/board/ti/am62x_sk.rst +++ b/doc/board/ti/am62x_sk.rst @@ -230,6 +230,63 @@ Image formats: | +-------------------+ | +-----------------------+ +A53 SPL DDR Memory Layout +------------------------- + +This provides an overview memory usage in A53 SPL stage. + +.. list-table:: + :widths: 16 16 16 + :header-rows: 1 + + * - Region + - Start Address + - End Address + + * - EMPTY + - 0x80000000 + - 0x80080000 + + * - TEXT BASE + - 0x80080000 + - 0x800d8000 + + * - EMPTY + - 0x800d8000 + - 0x80200000 + + * - BMP IMAGE + - 0x80200000 + - 0x80b77660 + + * - STACK + - 0x80b77660 + - 0x80b77e60 + + * - GD + - 0x80b77e60 + - 0x80b78000 + + * - MALLOC + - 0x80b78000 + - 0x80b80000 + + * - EMPTY + - 0x80b80000 + - 0x80c80000 + + * - BSS + - 0x80c80000 + - 0x80d00000 + + * - BLOBS + - 0x80d00000 + - 0x80d00400 + + * - EMPTY + - 0x80d00400 + - 0x81000000 + Switch Setting for Boot Mode ---------------------------- |