Exynos5420: Remove code for enabling read leveling

This patch intends to remove all code which enables hardware read
leveling. All characterization environments may not cope up with
h/w read leveling enabled, so we must disable this.
Also, disabling h/w read leveling improves the MIF LVcc value
(LVcc value is the value at which DDR will fail to work properly).
Improving LVcc means we have enough voltage margin for MIF.
When h/w leveling is enabled, we have almost zero volatge margin.

Signed-off-by: Alim Akhtar <[email protected]>
Signed-off-by: Akshay Saraswat <[email protected]>
Acked-by: Simon Glass <[email protected]>
Tested-by: Simon Glass <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>

1 files changed, 0 insertions, 71 deletions

diff --git a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
index 4481ab46bff..1d6048cbfcc 100644
--- a/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
+++ b/arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c
@@ -519,77 +519,6 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset)
 			       &drex1->directcmd);
 		}
 
-		if (mem->read_leveling_enable) {
-			/* Set Read DQ Calibration */
-			val = (0x3 << DIRECT_CMD_BANK_SHIFT) | 0x4;
-			for (chip = 0; chip < mem->chips_to_configure; chip++) {
-				writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
-				       &drex0->directcmd);
-				writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
-				       &drex1->directcmd);
-			}
-
-			val = readl(&phy0_ctrl->phy_con1);
-			val |= READ_LEVELLING_DDR3;
-			writel(val, &phy0_ctrl->phy_con1);
-			val = readl(&phy1_ctrl->phy_con1);
-			val |= READ_LEVELLING_DDR3;
-			writel(val, &phy1_ctrl->phy_con1);
-
-			val = readl(&phy0_ctrl->phy_con2);
-			val |= (RDLVL_EN | RDLVL_INCR_ADJ);
-			writel(val, &phy0_ctrl->phy_con2);
-			val = readl(&phy1_ctrl->phy_con2);
-			val |= (RDLVL_EN | RDLVL_INCR_ADJ);
-			writel(val, &phy1_ctrl->phy_con2);
-
-			setbits_le32(&drex0->rdlvl_config,
-				     CTRL_RDLVL_DATA_ENABLE);
-			i = TIMEOUT;
-			while (((readl(&drex0->phystatus) & RDLVL_COMPLETE_CHO)
-				 != RDLVL_COMPLETE_CHO) && (i > 0)) {
-				/*
-				 * TODO(waihong): Comment on how long this take
-				 * to timeout
-				 */
-				sdelay(100);
-				i--;
-			}
-			if (!i)
-				return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
-
-			clrbits_le32(&drex0->rdlvl_config,
-				     CTRL_RDLVL_DATA_ENABLE);
-			setbits_le32(&drex1->rdlvl_config,
-				     CTRL_RDLVL_DATA_ENABLE);
-			i = TIMEOUT;
-			while (((readl(&drex1->phystatus) & RDLVL_COMPLETE_CHO)
-				 != RDLVL_COMPLETE_CHO) && (i > 0)) {
-				/*
-				 * TODO(waihong): Comment on how long this take
-				 * to timeout
-				 */
-				sdelay(100);
-				i--;
-			}
-			if (!i)
-				return SETUP_ERR_RDLV_COMPLETE_TIMEOUT;
-
-			clrbits_le32(&drex1->rdlvl_config,
-				     CTRL_RDLVL_DATA_ENABLE);
-
-			val = (0x3 << DIRECT_CMD_BANK_SHIFT);
-			for (chip = 0; chip < mem->chips_to_configure; chip++) {
-				writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
-				       &drex0->directcmd);
-				writel(val | (chip << DIRECT_CMD_CHIP_SHIFT),
-				       &drex1->directcmd);
-			}
-
-			update_reset_dll(&drex0->phycontrol0, DDR_MODE_DDR3);
-			update_reset_dll(&drex1->phycontrol0, DDR_MODE_DDR3);
-		}
-
 		/* Common Settings for Leveling */
 		val = PHY_CON12_RESET_VAL;
 		writel((val + n_lock_w_phy0), &phy0_ctrl->phy_con12);