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authorMichal Simek <[email protected]>2025-11-10 13:33:33 +0100
committerMichal Simek <[email protected]>2025-12-19 08:25:26 +0100
commitac9494e96bd07a78d0f22ed24a03b06ba1f7b77d (patch)
treeabf14a50f6b6f6b98afc3c8f1e3195a188c07a09
parent2b7255cfa06ccd967583b035622476a42043131e (diff)
clk: versal: Cleanup driver
Remove unneeded debug messages, parenthesis and fix error message. Signed-off-by: Michal Simek <[email protected]> Link: https://lore.kernel.org/r/5b6fbcff1025415adc97e3e17eeb18863df4383e.1762778011.git.michal.simek@amd.com
-rw-r--r--drivers/clk/clk_versal.c9
1 files changed, 2 insertions, 7 deletions
diff --git a/drivers/clk/clk_versal.c b/drivers/clk/clk_versal.c
index ddaff07de0f..4a498e22f96 100644
--- a/drivers/clk/clk_versal.c
+++ b/drivers/clk/clk_versal.c
@@ -719,8 +719,6 @@ static ulong versal_clk_get_rate(struct clk *clk)
if (id >= clock_max_idx)
return -ENODEV;
- debug("%s\n", __func__);
-
clk_id = priv->clk[id].clk_id;
versal_clock_get_rate(clk_id, &clk_rate);
@@ -737,8 +735,6 @@ static ulong versal_clk_set_rate(struct clk *clk, ulong rate)
u32 div;
int ret;
- debug("%s\n", __func__);
-
if (id >= clock_max_idx)
return -ENODEV;
@@ -764,7 +760,7 @@ static ulong versal_clk_set_rate(struct clk *clk, ulong rate)
} while (((clk_id >> NODE_SUBCLASS_SHIFT) &
NODE_CLASS_MASK) != NODE_SUBCLASS_CLOCK_REF);
- printf("Clock didn't has Divisors:0x%x\n", priv->clk[id].clk_id);
+ printf("Clock has no divider: 0x%x\n", clk_id);
return clk_rate;
}
@@ -780,10 +776,9 @@ static int versal_clk_enable(struct clk *clk)
clk_id = priv->clk[id].clk_id;
- if (versal_clock_gate(clk_id)) {
+ if (versal_clock_gate(clk_id))
return xilinx_pm_request(PM_CLOCK_ENABLE, clk_id, 0, 0, 0,
0, 0, NULL);
- }
return 0;
}