diff options
| author | Andre Przywara <[email protected]> | 2022-09-05 16:25:57 +0100 |
|---|---|---|
| committer | Andre Przywara <[email protected]> | 2023-10-22 23:41:51 +0100 |
| commit | ad9dcb50019d3d87aa658079907451a3e371c687 (patch) | |
| tree | 6f2c45a89ceabac10b7abfe3f795ae16507b7d4d | |
| parent | 4a9e89a3e390bbff31aec25f9ec6d32e29e355f5 (diff) | |
pinctrl: sunxi: add Allwinner D1 pinctrl description
Apart from using the new pinctrl MMIO register layout, the Allwinner D1
and related SoCs still need to usual set of mux values hardcoded in
U-Boot's pinctrl driver.
Add the values we need so far to this list, so that DM based drivers
will just work without further ado.
Signed-off-by: Andre Przywara <[email protected]>
| -rw-r--r-- | drivers/pinctrl/sunxi/Kconfig | 4 | ||||
| -rw-r--r-- | drivers/pinctrl/sunxi/pinctrl-sunxi.c | 32 |
2 files changed, 36 insertions, 0 deletions
diff --git a/drivers/pinctrl/sunxi/Kconfig b/drivers/pinctrl/sunxi/Kconfig index 77da90836b6..c8f937d91e9 100644 --- a/drivers/pinctrl/sunxi/Kconfig +++ b/drivers/pinctrl/sunxi/Kconfig @@ -124,4 +124,8 @@ config PINCTRL_SUN50I_H616_R default MACH_SUN50I_H616 select PINCTRL_SUNXI +config PINCTRL_SUN20I_D1 + bool "Support for the Allwinner D1/R528 PIO" + select PINCTRL_SUNXI + endif diff --git a/drivers/pinctrl/sunxi/pinctrl-sunxi.c b/drivers/pinctrl/sunxi/pinctrl-sunxi.c index fc80fe50b14..bdf6360f176 100644 --- a/drivers/pinctrl/sunxi/pinctrl-sunxi.c +++ b/drivers/pinctrl/sunxi/pinctrl-sunxi.c @@ -598,6 +598,32 @@ static const struct sunxi_pinctrl_desc __maybe_unused sun9i_a80_r_pinctrl_desc = .num_banks = 3, }; +static const struct sunxi_pinctrl_function sun20i_d1_pinctrl_functions[] = { + { "emac", 8 }, /* PE0-PE15 */ + { "gpio_in", 0 }, + { "gpio_out", 1 }, + { "i2c0", 4 }, /* PB10-PB11 */ + { "mmc0", 2 }, /* PF0-PF5 */ + { "mmc1", 2 }, /* PG0-PG5 */ + { "mmc2", 3 }, /* PC2-PC7 */ + { "spi0", 2 }, /* PC2-PC7 */ +#if IS_ENABLED(CONFIG_UART0_PORT_F) + { "uart0", 3 }, /* PF2,PF4 */ +#else + { "uart0", 6 }, /* PB0-PB1, PB8-PB9, PE2-PE3 */ +#endif + { "uart1", 2 }, /* PG6-PG7 */ + { "uart2", 7 }, /* PB0-PB1 */ + { "uart3", 7 }, /* PB6-PB7 */ +}; + +static const struct sunxi_pinctrl_desc __maybe_unused sun20i_d1_pinctrl_desc = { + .functions = sun20i_d1_pinctrl_functions, + .num_functions = ARRAY_SIZE(sun20i_d1_pinctrl_functions), + .first_bank = SUNXI_GPIO_A, + .num_banks = 7, +}; + static const struct sunxi_pinctrl_function sun50i_a64_pinctrl_functions[] = { { "emac", 4 }, /* PD8-PD23 */ { "gpio_in", 0 }, @@ -863,6 +889,12 @@ static const struct udevice_id sunxi_pinctrl_ids[] = { .data = (ulong)&sun9i_a80_r_pinctrl_desc, }, #endif +#ifdef CONFIG_PINCTRL_SUN20I_D1 + { + .compatible = "allwinner,sun20i-d1-pinctrl", + .data = (ulong)&sun20i_d1_pinctrl_desc, + }, +#endif #ifdef CONFIG_PINCTRL_SUN50I_A64 { .compatible = "allwinner,sun50i-a64-pinctrl", |