diff options
| author | Joonyoung Shim <[email protected]> | 2015-01-23 17:30:07 +0900 |
|---|---|---|
| committer | Minkyu Kang <[email protected]> | 2015-02-13 17:19:48 +0900 |
| commit | b00f8edb5a1a98636afa121c7c8eacc9045ae19f (patch) | |
| tree | 18b41393dabb2d6408395ae847c3a405bc6ff219 | |
| parent | de3b251870780c8ed6406e15f3fcaf92a9e3c498 (diff) | |
odroid: fix g2d sclk rate
G2D core should be provided 200MHz clock rate.
Signed-off-by: Joonyoung Shim <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>
| -rw-r--r-- | board/samsung/odroid/odroid.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 306cc0f9d96..bff6ac928ca 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -248,12 +248,12 @@ static void board_clock_init(void) * MOUTc2c = 800 Mhz * MOUTpwi = 108 MHz * - * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 400 (1) + * sclk_g2d_acp = MOUTg2d / (ratio + 1) = 200 (3) * sclk_c2c = MOUTc2c / (ratio + 1) = 400 (1) * aclk_c2c = sclk_c2c / (ratio + 1) = 200 (1) * sclk_pwi = MOUTpwi / (ratio + 1) = 18 (5) */ - set = G2D_ACP_RATIO(1) | C2C_RATIO(1) | PWI_RATIO(5) | + set = G2D_ACP_RATIO(3) | C2C_RATIO(1) | PWI_RATIO(5) | C2C_ACLK_RATIO(1) | DVSEM_RATIO(1) | DPM_RATIO(1); clrsetbits_le32(&clk->div_dmc1, clr, set); |