diff options
| author | Quentin Schulz <[email protected]> | 2026-02-03 10:58:06 +0100 |
|---|---|---|
| committer | Tom Rini <[email protected]> | 2026-03-10 10:07:03 -0600 |
| commit | b107cfbb794e3c6dc32fc8de176220960207fe68 (patch) | |
| tree | 09bc201029d95bd0ea3fd475690456580db74a41 | |
| parent | 52877548d38ddb9e218347066187606d96767621 (diff) | |
rockchip: rk3588: include all addressable DRAM in memory map
The ATAGS set by Rockchip DDR init blob[1] specify DRAM banks above the
first addressable 4GiB which we haven't done in the mem_map for RK3588
yet.
For 4GiB DRAM, the 256MiB missing from the first addressable 4GiB (due
to MMIO) are accessible at the end of the 8GiB address space. For 8GiB,
4-8GiB address space is used for the additional 4GiB and the missing
256MiB are at the end of 12GiB address space. For 12, 4-12GiB and the
missing 256MiB at the end of 20GiB address space. For 16GiB, 4-~16GiB
with two holes (reasons unknown) around 16GiB and the missing 256MiB is
at the end of 20GiB address space. For 32GiB, 4-16~GiB with two holes
and then 16GiB to 32GiB address space (so likely missing 256MiB from
MMIO address space).
[1] https://gist.github.com/Kwiboo/1c020d37e3adbc9d0d79dc003d921977
Suggested-by: Jonas Karlman <[email protected]>
Signed-off-by: Quentin Schulz <[email protected]>
Reviewed-by: Kever Yang <[email protected]>
| -rw-r--r-- | arch/arm/mach-rockchip/rk3588/rk3588.c | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index c1138ffcb87..eedce7b9b08 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -88,6 +88,24 @@ static struct mm_region rk3588_mem_map[] = { PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, { + .virt = 0x100000000UL, + .phys = 0x100000000UL, + .size = 0x2fc000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x3fc500000UL, + .phys = 0x3fc500000UL, + .size = 0x3a00000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x400000000UL, + .phys = 0x400000000UL, + .size = 0x400000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { .virt = 0x900000000, .phys = 0x900000000, .size = 0x150000000, |